Merge tag 'imx35-imx5-aips-setup' of git://git.pengutronix.de/git/imx/linux-2.6 into...

i.MX35/5 AIPS setup

Includes sync up to 3.3-rc6

* tag 'imx35-imx5-aips-setup' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: mx35: Setup the AIPS registers
  ARM: mx5: Use common function for configuring AIPS

diff --combined arch/arm/mach-imx/mm-imx3.c
index b23bd3f09a60a1dee7c98e0f65ee1eddf7c27c9d,d0c835c85b939ad661109f0867b7de5d04f4e463..2215814c8c2cfd6646c2b65de77507f473b6e1f4
--- 1/arch/arm/mach-imx/mm-imx3.c
--- 2/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -34,31 -34,31 +34,31 @@@ static void imx3_idle(void
  {
        unsigned long reg = 0;
  
 -      if (!need_resched())
 -              __asm__ __volatile__(
 -                      /* disable I and D cache */
 -                      "mrc p15, 0, %0, c1, c0, 0\n"
 -                      "bic %0, %0, #0x00001000\n"
 -                      "bic %0, %0, #0x00000004\n"
 -                      "mcr p15, 0, %0, c1, c0, 0\n"
 -                      /* invalidate I cache */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c5, 0\n"
 -                      /* clear and invalidate D cache */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c14, 0\n"
 -                      /* WFI */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c0, 4\n"
 -                      "nop\n" "nop\n" "nop\n" "nop\n"
 -                      "nop\n" "nop\n" "nop\n"
 -                      /* enable I and D cache */
 -                      "mrc p15, 0, %0, c1, c0, 0\n"
 -                      "orr %0, %0, #0x00001000\n"
 -                      "orr %0, %0, #0x00000004\n"
 -                      "mcr p15, 0, %0, c1, c0, 0\n"
 -                      : "=r" (reg));
 -      local_irq_enable();
 +      mx3_cpu_lp_set(MX3_WAIT);
 +
 +      __asm__ __volatile__(
 +              /* disable I and D cache */
 +              "mrc p15, 0, %0, c1, c0, 0\n"
 +              "bic %0, %0, #0x00001000\n"
 +              "bic %0, %0, #0x00000004\n"
 +              "mcr p15, 0, %0, c1, c0, 0\n"
 +              /* invalidate I cache */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c5, 0\n"
 +              /* clear and invalidate D cache */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c14, 0\n"
 +              /* WFI */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c0, 4\n"
 +              "nop\n" "nop\n" "nop\n" "nop\n"
 +              "nop\n" "nop\n" "nop\n"
 +              /* enable I and D cache */
 +              "mrc p15, 0, %0, c1, c0, 0\n"
 +              "orr %0, %0, #0x00001000\n"
 +              "orr %0, %0, #0x00000004\n"
 +              "mcr p15, 0, %0, c1, c0, 0\n"
 +              : "=r" (reg));
  }
  
  static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@@ -134,8 -134,8 +134,8 @@@ void __init imx31_init_early(void
  {
        mxc_set_cpu_type(MXC_CPU_MX31);
        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 -      pm_idle = imx3_idle;
        imx_ioremap = imx3_ioremap;
 +      arm_pm_idle = imx3_idle;
  }
  
  void __init mx31_init_irq(void)
@@@ -175,9 -175,6 +175,9 @@@ void __init imx31_soc_init(void
        }
  
        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
 +
 +      imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
 +      imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
  }
  #endif /* ifdef CONFIG_SOC_IMX31 */
  
@@@ -200,7 -197,7 +200,7 @@@ void __init imx35_init_early(void
        mxc_set_cpu_type(MXC_CPU_MX35);
        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 -      pm_idle = imx3_idle;
 +      arm_pm_idle = imx3_idle;
        imx_ioremap = imx3_ioremap;
  }
  
@@@ -262,5 -259,9 +262,9 @@@ void __init imx35_soc_init(void
        }
  
        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+ 
+       /* Setup AIPS registers */
+       imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
+       imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
  }
  #endif /* ifdef CONFIG_SOC_IMX35 */

diff --combined arch/arm/mach-imx/mm-imx5.c
index 49549a72dc7dbb2de0c8d1e75af06deddbef2a59,93826eb01560b7752acb6f3e9d594a97d89008ea..92efecec12608af2095d6c0c8e75a62df6f987d0
--- 1/arch/arm/mach-imx/mm-imx5.c
--- 2/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@@ -26,17 -26,23 +26,17 @@@ static struct clk *gpc_dvfs_clk
  
  static void imx5_idle(void)
  {
 -      if (!need_resched()) {
 -              /* gpc clock is needed for SRPG */
 -              if (gpc_dvfs_clk == NULL) {
 -                      gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 -                      if (IS_ERR(gpc_dvfs_clk))
 -                              goto err0;
 -              }
 -              clk_enable(gpc_dvfs_clk);
 -              mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
 -              if (tzic_enable_wake())
 -                      goto err1;
 -              cpu_do_idle();
 -err1:
 -              clk_disable(gpc_dvfs_clk);
 +      /* gpc clock is needed for SRPG */
 +      if (gpc_dvfs_clk == NULL) {
 +              gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 +              if (IS_ERR(gpc_dvfs_clk))
 +                      return;
        }
 -err0:
 -      local_irq_enable();
 +      clk_enable(gpc_dvfs_clk);
 +      mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
 +      if (tzic_enable_wake() != 0)
 +              cpu_do_idle();
 +      clk_disable(gpc_dvfs_clk);
  }
  
  /*
@@@ -102,7 -108,7 +102,7 @@@ void __init imx51_init_early(void
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
 -      pm_idle = imx5_idle;
 +      arm_pm_idle = imx5_idle;
  }
  
  void __init imx53_init_early(void)
@@@ -185,6 -191,10 +185,10 @@@ void __init imx51_soc_init(void
  
        /* i.mx51 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+ 
+       /* Setup AIPS registers */
+       imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
+       imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
  }
  
  void __init imx53_soc_init(void)
@@@ -200,4 -210,8 +204,8 @@@
  
        /* i.mx53 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+ 
+       /* Setup AIPS registers */
+       imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
+       imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
  }

diff --combined arch/arm/mach-omap2/io.c
index 5f8c4e1a3fb9d30baa010155b5a46187fcd5ec52,fb11b44fbdecc77d6c8b5ce41e5da4f0aeecc1fc..168fd120772b46f4e6f839f473107ea3e38604bf
--- 1/arch/arm/mach-omap2/io.c
--- 2/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@@ -307,6 -307,7 +307,7 @@@ void __init omapam33xx_map_common_io(vo
  void __init omap44xx_map_common_io(void)
  {
        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
+       omap_barriers_init();
  }
  #endif
  
@@@ -351,6 -352,7 +352,6 @@@ static int _set_hwmod_postsetup_state(s
  
  static void __init omap_common_init_early(void)
  {
 -      omap2_check_revision();
        omap_init_consistent_dma_size();
  }
  
@@@ -391,7 -393,6 +392,7 @@@ static void __init omap_hwmod_init_post
  void __init omap2420_init_early(void)
  {
        omap2_set_globals_242x();
 +      omap2xxx_check_revision();
        omap_common_init_early();
        omap2xxx_voltagedomains_init();
        omap242x_powerdomains_init();
@@@ -406,7 -407,6 +407,7 @@@
  void __init omap2430_init_early(void)
  {
        omap2_set_globals_243x();
 +      omap2xxx_check_revision();
        omap_common_init_early();
        omap2xxx_voltagedomains_init();
        omap243x_powerdomains_init();
@@@ -425,8 -425,6 +426,8 @@@
  void __init omap3_init_early(void)
  {
        omap2_set_globals_3xxx();
 +      omap3xxx_check_revision();
 +      omap3xxx_check_features();
        omap_common_init_early();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
@@@ -459,8 -457,6 +460,8 @@@ void __init am35xx_init_early(void
  void __init ti81xx_init_early(void)
  {
        omap2_set_globals_ti81xx();
 +      omap3xxx_check_revision();
 +      ti81xx_check_features();
        omap_common_init_early();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
@@@ -475,8 -471,6 +476,8 @@@
  void __init omap4430_init_early(void)
  {
        omap2_set_globals_443x();
 +      omap4xxx_check_revision();
 +      omap4xxx_check_features();
        omap_common_init_early();
        omap44xx_voltagedomains_init();
        omap44xx_powerdomains_init();