Merge tag 'x86_cache_for_v6.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 resource control updates from Borislav Petkov:

 - Add support for a new AMD feature called slow memory bandwidth
   allocation. Its goal is to control resource allocation in external
   slow memory which is connected to the machine like for example
   through CXL devices, accelerators etc

* tag 'x86_cache_for_v6.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/resctrl: Fix a silly -Wunused-but-set-variable warning
  Documentation/x86: Update resctrl.rst for new features
  x86/resctrl: Add interface to write mbm_local_bytes_config
  x86/resctrl: Add interface to write mbm_total_bytes_config
  x86/resctrl: Add interface to read mbm_local_bytes_config
  x86/resctrl: Add interface to read mbm_total_bytes_config
  x86/resctrl: Support monitor configuration
  x86/resctrl: Add __init attribute to rdt_get_mon_l3_config()
  x86/resctrl: Detect and configure Slow Memory Bandwidth Allocation
  x86/resctrl: Include new features in command line options
  x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag
  x86/resctrl: Add a new resource type RDT_RESOURCE_SMBA
  x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag
  x86/resctrl: Replace smp_call_function_many() with on_each_cpu_mask()

diff --combined arch/x86/include/asm/cpufeatures.h
index dba52f43c8a1175be119be28de0b40f0d28f19db,f6a41ec42fd7550cb293fb2d405a8bdb0a774263..49973061b5bdefd8e6d4ae3702f7eeefe44b74cd
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -307,12 -307,13 +307,14 @@@
  #define X86_FEATURE_SGX_EDECCSSA      (11*32+18) /* "" SGX EDECCSSA user leaf function */
  #define X86_FEATURE_CALL_DEPTH                (11*32+19) /* "" Call depth tracking for RSB stuffing */
  #define X86_FEATURE_MSR_TSX_CTRL      (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
+ #define X86_FEATURE_SMBA              (11*32+21) /* "" Slow Memory Bandwidth Allocation */
+ #define X86_FEATURE_BMEC              (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
  
  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
  #define X86_FEATURE_AVX_VNNI          (12*32+ 4) /* AVX VNNI instructions */
  #define X86_FEATURE_AVX512_BF16               (12*32+ 5) /* AVX512 BFLOAT16 instructions */
  #define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* "" CMPccXADD instructions */
 +#define X86_FEATURE_ARCH_PERFMON_EXT  (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
  #define X86_FEATURE_AMX_FP16          (12*32+21) /* "" AMX fp16 Support */
  #define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
  
@@@ -467,6 -468,5 +469,6 @@@
  #define X86_BUG_MMIO_UNKNOWN          X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
  #define X86_BUG_RETBLEED              X86_BUG(27) /* CPU is affected by RETBleed */
  #define X86_BUG_EIBRS_PBRSB           X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
 +#define X86_BUG_SMT_RSB                       X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */
  
  #endif /* _ASM_X86_CPUFEATURES_H */

diff --combined arch/x86/include/asm/msr-index.h
index c88dd9d3fa0847a68a825251c4a8cad7c7ec67f0,2e5f57c936051272f09aee87daeb182fecaafb66..28d334fa85881c9f63357dcd18f8dd153f94456d
--- 1/arch/x86/include/asm/msr-index.h
--- 2/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -189,9 -189,6 +189,9 @@@
  #define MSR_TURBO_RATIO_LIMIT1                0x000001ae
  #define MSR_TURBO_RATIO_LIMIT2                0x000001af
  
 +#define MSR_SNOOP_RSP_0                       0x00001328
 +#define MSR_SNOOP_RSP_1                       0x00001329
 +
  #define MSR_LBR_SELECT                        0x000001c8
  #define MSR_LBR_TOS                   0x000001c9
  
@@@ -569,26 -566,6 +569,26 @@@
  #define MSR_AMD64_SEV_ES_ENABLED      BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
  #define MSR_AMD64_SEV_SNP_ENABLED     BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
  
 +/* SNP feature bits enabled by the hypervisor */
 +#define MSR_AMD64_SNP_VTOM                    BIT_ULL(3)
 +#define MSR_AMD64_SNP_REFLECT_VC              BIT_ULL(4)
 +#define MSR_AMD64_SNP_RESTRICTED_INJ          BIT_ULL(5)
 +#define MSR_AMD64_SNP_ALT_INJ                 BIT_ULL(6)
 +#define MSR_AMD64_SNP_DEBUG_SWAP              BIT_ULL(7)
 +#define MSR_AMD64_SNP_PREVENT_HOST_IBS                BIT_ULL(8)
 +#define MSR_AMD64_SNP_BTB_ISOLATION           BIT_ULL(9)
 +#define MSR_AMD64_SNP_VMPL_SSS                        BIT_ULL(10)
 +#define MSR_AMD64_SNP_SECURE_TSC              BIT_ULL(11)
 +#define MSR_AMD64_SNP_VMGEXIT_PARAM           BIT_ULL(12)
 +#define MSR_AMD64_SNP_IBS_VIRT                        BIT_ULL(14)
 +#define MSR_AMD64_SNP_VMSA_REG_PROTECTION     BIT_ULL(16)
 +#define MSR_AMD64_SNP_SMT_PROTECTION          BIT_ULL(17)
 +
 +/* SNP feature bits reserved for future use. */
 +#define MSR_AMD64_SNP_RESERVED_BIT13          BIT_ULL(13)
 +#define MSR_AMD64_SNP_RESERVED_BIT15          BIT_ULL(15)
 +#define MSR_AMD64_SNP_RESERVED_MASK           GENMASK_ULL(63, 18)
 +
  #define MSR_AMD64_VIRT_SPEC_CTRL      0xc001011f
  
  /* AMD Collaborative Processor Performance Control MSRs */
@@@ -1084,6 -1061,8 +1084,8 @@@
  
  /* - AMD: */
  #define MSR_IA32_MBA_BW_BASE          0xc0000200
+ #define MSR_IA32_SMBA_BW_BASE         0xc0000280
+ #define MSR_IA32_EVT_CFG_BASE         0xc0000400
  
  /* MSR_IA32_VMX_MISC bits */
  #define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)