Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

Pull timer core updates from Thomas Gleixner:
 "The time(r) departement provides:

   - more infrastructure work on the year 2038 issue

   - a few fixes in the Armada SoC timers

   - the usual pile of fixlets and improvements"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  clocksource: armada-370-xp: Use the reference clock on A375 SoC
  watchdog: orion: Use the reference clock on Armada 375 SoC
  clocksource: armada-370-xp: Add missing clock enable
  time: Fix sign bug in NTP mult overflow warning
  time: Remove timekeeping_inject_sleeptime()
  rtc: Update suspend/resume timing to use 64bit time
  rtc/lib: Provide y2038 safe rtc_tm_to_time()/rtc_time_to_tm() replacement
  time: Fixup comments to reflect usage of timespec64
  time: Expose get_monotonic_coarse64() for in-kernel uses
  time: Expose getrawmonotonic64 for in-kernel uses
  time: Provide y2038 safe mktime() replacement
  time: Provide y2038 safe timekeeping_inject_sleeptime() replacement
  time: Provide y2038 safe do_settimeofday() replacement
  time: Complete NTP adjustment threshold judging conditions
  time: Avoid possible NTP adjustment mult overflow.
  time: Rename udelay_test.c to test_udelay.c
  clocksource: sirf: Remove hard-coded clock rate

diff --combined drivers/clocksource/time-armada-370-xp.c
index ff37d3abb80625e0af9f792d840b766015080b7a,3a0704b0d7398110ba13a7fd7c37fb75a25fffb6..0c8c5e3375407fad8c6f666c596d1b2c155acc04
--- 1/drivers/clocksource/time-armada-370-xp.c
--- 2/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@@ -43,7 -43,6 +43,7 @@@
  #include <linux/module.h>
  #include <linux/sched_clock.h>
  #include <linux/percpu.h>
 +#include <linux/syscore_ops.h>
  
  /*
   * Timer block registers.
@@@ -224,28 -223,6 +224,28 @@@ static struct notifier_block armada_370
        .notifier_call = armada_370_xp_timer_cpu_notify,
  };
  
 +static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
 +
 +static int armada_370_xp_timer_suspend(void)
 +{
 +      timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
 +      timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
 +      return 0;
 +}
 +
 +static void armada_370_xp_timer_resume(void)
 +{
 +      writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 +      writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 +      writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
 +      writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
 +}
 +
 +struct syscore_ops armada_370_xp_timer_syscore_ops = {
 +      .suspend        = armada_370_xp_timer_suspend,
 +      .resume         = armada_370_xp_timer_resume,
 +};
 +
  static void __init armada_370_xp_timer_common_init(struct device_node *np)
  {
        u32 clr = 0, set = 0;
@@@ -308,8 -285,6 +308,8 @@@
        /* Immediately configure the timer on the boot CPU */
        if (!res)
                armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 +
 +      register_syscore_ops(&armada_370_xp_timer_syscore_ops);
  }
  
  static void __init armada_xp_timer_init(struct device_node *np)
@@@ -318,6 -293,7 +318,7 @@@
  
        /* The 25Mhz fixed clock is mandatory, and must always be available */
        BUG_ON(IS_ERR(clk));
+       clk_prepare_enable(clk);
        timer_clk = clk_get_rate(clk);
  
        armada_370_xp_timer_common_init(np);
@@@ -325,11 -301,40 +326,40 @@@
  CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
                       armada_xp_timer_init);
  
+ static void __init armada_375_timer_init(struct device_node *np)
+ {
+       struct clk *clk;
+ 
+       clk = of_clk_get_by_name(np, "fixed");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               timer_clk = clk_get_rate(clk);
+       } else {
+ 
+               /*
+                * This fallback is required in order to retain proper
+                * devicetree backwards compatibility.
+                */
+               clk = of_clk_get(np, 0);
+ 
+               /* Must have at least a clock */
+               BUG_ON(IS_ERR(clk));
+               clk_prepare_enable(clk);
+               timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
+               timer25Mhz = false;
+       }
+ 
+       armada_370_xp_timer_common_init(np);
+ }
+ CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
+                      armada_375_timer_init);
+ 
  static void __init armada_370_timer_init(struct device_node *np)
  {
        struct clk *clk = of_clk_get(np, 0);
  
        BUG_ON(IS_ERR(clk));
+       clk_prepare_enable(clk);
        timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
        timer25Mhz = false;