drm/msm/dpu: drop MSM_ENC_VBLANK support

There are no in-kernel users of MSM_ENC_VBLANK wait type. Drop it
together with the corresponding wait_for_vblank callback.

Reviewed-by: Abhinav Kumar <[email protected]>
Patchwork: https://patchwork.freedesktop.org/patch/560701/
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dmitry Baryshkov <[email protected]>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index aa1a1646b322abce3439812cde6a003831d19986..889e9bb42715f50364b003f736fb049ed5e5d178 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2400,9 +2400,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
                case MSM_ENC_TX_COMPLETE:
                        fn_wait = phys->ops.wait_for_tx_complete;
                        break;
-               case MSM_ENC_VBLANK:
-                       fn_wait = phys->ops.wait_for_vblank;
-                       break;
                default:
                        DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
                                        event);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index b6b48e2c63efa6c60ed409f2704059832f4d0c1e..e2934a6702d1ced40fc9756e50684b5914bc9211 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -104,7 +104,6 @@ struct dpu_encoder_phys_ops {
        int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
        int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
        int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
-       int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
        void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
        void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
        void (*trigger_start)(struct dpu_encoder_phys *phys_enc);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index d24f45d1f654f89721e36c436b78f4e77bbdb58e..76f1f66e41cd0722592c02cbb4c2cb6fdc1e32ab 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -675,33 +675,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done(
        return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
 }
 
-static int dpu_encoder_phys_cmd_wait_for_vblank(
-               struct dpu_encoder_phys *phys_enc)
-{
-       int rc = 0;
-       struct dpu_encoder_phys_cmd *cmd_enc;
-       struct dpu_encoder_wait_info wait_info;
-
-       cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
-
-       /* only required for master controller */
-       if (!dpu_encoder_phys_cmd_is_master(phys_enc))
-               return rc;
-
-       wait_info.wq = &cmd_enc->pending_vblank_wq;
-       wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
-       wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
-
-       atomic_inc(&cmd_enc->pending_vblank_cnt);
-
-       rc = dpu_encoder_helper_wait_for_irq(phys_enc,
-                       phys_enc->irq[INTR_IDX_RDPTR],
-                       dpu_encoder_phys_cmd_te_rd_ptr_irq,
-                       &wait_info);
-
-       return rc;
-}
-
 static void dpu_encoder_phys_cmd_handle_post_kickoff(
                struct dpu_encoder_phys *phys_enc)
 {
@@ -729,7 +702,6 @@ static void dpu_encoder_phys_cmd_init_ops(
        ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;
        ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;
        ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;
-       ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
        ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
        ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
        ops->irq_control = dpu_encoder_phys_cmd_irq_control;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 69bc1b2e514cc16c6137609b4c178c2fde97f5a4..2b4e5b5eff44782e947ded43230218b6f3135054 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -440,7 +440,7 @@ skip_flush:
                phys_enc->enable_state = DPU_ENC_ENABLING;
 }
 
-static int dpu_encoder_phys_vid_wait_for_vblank(
+static int dpu_encoder_phys_vid_wait_for_tx_complete(
                struct dpu_encoder_phys *phys_enc)
 {
        struct dpu_encoder_wait_info wait_info;
@@ -554,7 +554,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
         * scanout buffer) don't latch properly..
         */
        if (dpu_encoder_phys_vid_is_master(phys_enc)) {
-               ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+               ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
                if (ret) {
                        atomic_set(&phys_enc->pending_kickoff_cnt, 0);
                        DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
@@ -574,7 +574,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
                spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
                dpu_encoder_phys_inc_pending(phys_enc);
                spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-               ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+               ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
                if (ret) {
                        atomic_set(&phys_enc->pending_kickoff_cnt, 0);
                        DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
@@ -679,8 +679,7 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
        ops->disable = dpu_encoder_phys_vid_disable;
        ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
        ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
-       ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
-       ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
+       ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
        ops->irq_control = dpu_encoder_phys_vid_irq_control;
        ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
        ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index a205127ccc932f6bfd8a5a7dd56d7c0cb84da15c..c0446fa66b98d08dad853a750011bb659644f7ba 100644 (file)
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -78,12 +78,10 @@ enum msm_dsi_controller {
  * enum msm_event_wait - type of HW events to wait for
  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
- * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  */
 enum msm_event_wait {
        MSM_ENC_COMMIT_DONE = 0,
        MSM_ENC_TX_COMPLETE,
-       MSM_ENC_VBLANK,
 };
 
 /**