clk: socfpga: agilex: fix the parents of the psi_ref_clk

The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.

Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: [email protected]
Signed-off-by: Kris Chaplin <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 1cb21ea79c640d960ad00e18b89595ee2bf2e5ea..9dffe9ba0e740f9e87568b7cb00126d6fd8092ca 100644 (file)
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = {
 };
 
 static const struct clk_parent_data psi_ref_free_mux[] = {
-       { .fw_name = "main_pll_c3",
-         .name = "main_pll_c3", },
-       { .fw_name = "peri_pll_c3",
-         .name = "peri_pll_c3", },
+       { .fw_name = "main_pll_c2",
+         .name = "main_pll_c2", },
+       { .fw_name = "peri_pll_c2",
+         .name = "peri_pll_c2", },
        { .fw_name = "osc1",
          .name = "osc1", },
        { .fw_name = "cb-intosc-hs-div2-clk",