x86/resctrl: Move MSR defines into msr-index.h

msr-index.h should contain all MSRs for easier grepping for MSR numbers
when dealing with unchecked MSR access warnings, for example.

Move the resctrl ones. Prefix IA32_PQR_ASSOC with "MSR_" while at it.

No functional changes.

Signed-off-by: Borislav Petkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 10ac52705892a1680415d144877574a2457f0344..9308eb9eaf368aef5fe1201b1731a01b3e8f0d8f 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -4,12 +4,7 @@
 
 #include <linux/bits.h>
 
-/*
- * CPU model specific register (MSR) numbers.
- *
- * Do not add new entries to this file unless the definitions are shared
- * between multiple compilation units.
- */
+/* CPU model specific register (MSR) numbers. */
 
 /* x86-64 specific MSRs */
 #define MSR_EFER               0xc0000080 /* extended feature register */
@@ -1050,6 +1045,20 @@
 #define VMX_BASIC_MEM_TYPE_WB  6LLU
 #define VMX_BASIC_INOUT                0x0040000000000000LLU
 
+/* Resctrl MSRs: */
+/* - Intel: */
+#define MSR_IA32_L3_QOS_CFG            0xc81
+#define MSR_IA32_L2_QOS_CFG            0xc82
+#define MSR_IA32_QM_EVTSEL             0xc8d
+#define MSR_IA32_QM_CTR                        0xc8e
+#define MSR_IA32_PQR_ASSOC             0xc8f
+#define MSR_IA32_L3_CBM_BASE           0xc90
+#define MSR_IA32_L2_CBM_BASE           0xd10
+#define MSR_IA32_MBA_THRTL_BASE                0xd50
+
+/* - AMD: */
+#define MSR_IA32_MBA_BW_BASE           0xc0000200
+
 /* MSR_IA32_VMX_MISC bits */
 #define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)

diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h
index d24b04ebf950ed1a78952317e8af262e9681c67d..52788f79786fad74f2c373e5ce7895e79af26942 100644 (file)
--- a/arch/x86/include/asm/resctrl.h
+++ b/arch/x86/include/asm/resctrl.h
@@ -7,8 +7,6 @@
 #include <linux/sched.h>
 #include <linux/jump_label.h>
 
-#define IA32_PQR_ASSOC 0x0c8f
-
 /**
  * struct resctrl_pqr_state - State cache for the PQR MSR
  * @cur_rmid:          The cached Resource Monitoring ID
@@ -16,8 +14,8 @@
  * @default_rmid:      The user assigned Resource Monitoring ID
  * @default_closid:    The user assigned cached Class Of Service ID
  *
- * The upper 32 bits of IA32_PQR_ASSOC contain closid and the
- * lower 10 bits rmid. The update to IA32_PQR_ASSOC always
+ * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
+ * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
  * contains both parts, so we need to cache them. This also
  * stores the user configured per cpu CLOSID and RMID.
  *
@@ -77,7 +75,7 @@ static void __resctrl_sched_in(void)
        if (closid != state->cur_closid || rmid != state->cur_rmid) {
                state->cur_closid = closid;
                state->cur_rmid = rmid;
-               wrmsr(IA32_PQR_ASSOC, rmid, closid);
+               wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid);
        }
 }
 

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 03cfbf0fe0000b13672482ce744d9bec49121472..c98e52ff5f206267c2a097eef4c443b47b3c6272 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -575,7 +575,7 @@ static void clear_closid_rmid(int cpu)
        state->default_rmid = 0;
        state->cur_closid = 0;
        state->cur_rmid = 0;
-       wrmsr(IA32_PQR_ASSOC, 0, 0);
+       wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
 }
 
 static int resctrl_online_cpu(unsigned int cpu)

diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
index 5f7128686cfd2f851b92707afedd6e7d313dfeab..5ebd28e6aa0cae5553f02f8092bf0463f08712f1 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/internal.h
+++ b/arch/x86/kernel/cpu/resctrl/internal.h
@@ -8,16 +8,6 @@
 #include <linux/fs_context.h>
 #include <linux/jump_label.h>
 
-#define MSR_IA32_L3_QOS_CFG            0xc81
-#define MSR_IA32_L2_QOS_CFG            0xc82
-#define MSR_IA32_L3_CBM_BASE           0xc90
-#define MSR_IA32_L2_CBM_BASE           0xd10
-#define MSR_IA32_MBA_THRTL_BASE                0xd50
-#define MSR_IA32_MBA_BW_BASE           0xc0000200
-
-#define MSR_IA32_QM_CTR                        0x0c8e
-#define MSR_IA32_QM_EVTSEL             0x0c8d
-
 #define L3_QOS_CDP_ENABLE              0x01ULL
 
 #define L2_QOS_CDP_ENABLE              0x01ULL

diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index d961ae3ed96e720e1a346bf1775abee9bfbe83a5..ba8d0763b36bb177627f401997a40592beae3644 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -477,7 +477,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
         * pseudo-locked followed by reading of kernel memory to load it
         * into the cache.
         */
-       __wrmsr(IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
+       __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, rdtgrp->closid);
        /*
         * Cache was flushed earlier. Now access kernel memory to read it
         * into cache region associated with just activated plr->closid.
@@ -513,7 +513,7 @@ static int pseudo_lock_fn(void *_rdtgrp)
         * Critical section end: restore closid with capacity bitmask that
         * does not overlap with pseudo-locked region.
         */
-       __wrmsr(IA32_PQR_ASSOC, rmid_p, closid_p);
+       __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
 
        /* Re-enable the hardware prefetcher(s) */
        wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr);