mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"

n25q512a was rebranded to mt25qu512a after its spin off from STM.
mt25qu512a is different only in terms of operating frequency, the
JEDEC id is the same as in n25q512a.

Dual reads are supported (0x3b, 0x3c), set the SPI_NOR_DUAL_READ flag.
4-byte opcodes are supported, set the SPI_NOR_4B_OPCODES flag.

Tested Single I/O and QUAD I/O mode on LS1046FRWY.

Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
[[email protected]: rename entry to "mt25qu512a (n25q512a)",
reword commit message, order entry by size, drop comment as it looked
redundant]
Signed-off-by: Tudor Ambarus <[email protected]>

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 2129cddc1a87bba4ff4095b883a9d58c8eacfe17..1d8621d43160de3da11a6ac668cd6f2654209807 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2309,13 +2309,16 @@ static const struct flash_info spi_nor_ids[] = {
        { "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
        { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
-       { "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
        { "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
        { "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
        { "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
        { "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
                              SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
                              NO_CHIP_ERASE) },
+       { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
+                                       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+                                       SPI_NOR_QUAD_READ |
+                                       SPI_NOR_4B_OPCODES) },
        { "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 
        /* Micron */