riscv: lib: relax assembly constraints in hweight

rd and rs don't have to be the same. In some cases where rs needs to be
saved for later usage, this will save us some mv instructions.

Signed-off-by: Qingfang Deng <[email protected]>
Reviewed-by: Xiao Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h
index 85b2c443823e8ab8ce55aa5b32953eabbc5e1108..613769b9cdc90025b15efc638be9611fbba6145b 100644 (file)
--- a/arch/riscv/include/asm/arch_hweight.h
+++ b/arch/riscv/include/asm/arch_hweight.h
@@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
 
        asm (".option push\n"
             ".option arch,+zbb\n"
-            CPOPW "%0, %0\n"
+            CPOPW "%0, %1\n"
             ".option pop\n"
-            : "+r" (w) : :);
+            : "=r" (w) : "r" (w) :);
 
        return w;
 
@@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
 
        asm (".option push\n"
             ".option arch,+zbb\n"
-            "cpop %0, %0\n"
+            "cpop %0, %1\n"
             ".option pop\n"
-            : "+r" (w) : :);
+            : "=r" (w) : "r" (w) :);
 
        return w;