arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS

Add the OPP table for the Mali Bifrost GPU and drop the hardcoded
initial clock configuration. This enables GPU DVFS and thus saves power
when the GPU is not in use while still being able switch to a higher
clock on demand.

Set the GP0_PLL clock to 744MHz (which is the only frequency which
cannot be derived from the FCLK dividers) as the clock driver avoids
setting the parent clock rates so the HIFI PLL clock isn't changed (as
that's reserved for audio).

Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 41805f2ed8fc188f053eb8850ef78c4c8b2fbd1d..1e83ec5b8c91a13018b3fc7a1651eca7f75290f7 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -52,6 +52,39 @@
                secure-monitor = <&sm>;
        };
 
+       gpu_opp_table: gpu-opp-table {
+               compatible = "operating-points-v2";
+
+               opp-124999998 {
+                       opp-hz = /bits/ 64 <124999998>;
+                       opp-microvolt = <800000>;
+               };
+               opp-249999996 {
+                       opp-hz = /bits/ 64 <249999996>;
+                       opp-microvolt = <800000>;
+               };
+               opp-285714281 {
+                       opp-hz = /bits/ 64 <285714281>;
+                       opp-microvolt = <800000>;
+               };
+               opp-399999994 {
+                       opp-hz = /bits/ 64 <399999994>;
+                       opp-microvolt = <800000>;
+               };
+               opp-499999992 {
+                       opp-hz = /bits/ 64 <499999992>;
+                       opp-microvolt = <800000>;
+               };
+               opp-666666656 {
+                       opp-hz = /bits/ 64 <666666656>;
+                       opp-microvolt = <800000>;
+               };
+               opp-799999987 {
+                       opp-hz = /bits/ 64 <799999987>;
+                       opp-microvolt = <800000>;
+               };
+       };
+
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
@@ -2362,21 +2395,7 @@
                        interrupt-names = "job", "mmu", "gpu";
                        clocks = <&clkc CLKID_MALI>;
                        resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
-
-                       /*
-                        * Mali clocking is provided by two identical clock paths
-                        * MALI_0 and MALI_1 muxed to a single clock by a glitch
-                        * free mux to safely change frequency while running.
-                        */
-                       assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
-                                         <&clkc CLKID_MALI_0>,
-                                         <&clkc CLKID_MALI>; /* Glitch free mux */
-                       assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
-                                                <0>, /* Do Nothing */
-                                                <&clkc CLKID_MALI_0>;
-                       assigned-clock-rates = <0>, /* Do Nothing */
-                                              <800000000>,
-                                              <0>; /* Do Nothing */
+                       operating-points-v2 = <&gpu_opp_table>;
                        #cooling-cells = <2>;
                };
        };