drm/i915: Agressive downclocking on Baytrail

Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.

v2: Rebase
v3: Exclude Cherrytrail as Deepak was concerned that the increased
number of register writes would wake the common powerwell too often.

Signed-off-by: Chris Wilson <[email protected]>
Cc: Deepak S <[email protected]>
Cc: Ville Syrjälä <[email protected]>
Cc: Rodrigo Vivi <[email protected]>
Cc: Daniel Vetter <[email protected]>
Reviewed-by: Deepak S <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 924676fdb26f1eb3ee8beb32f785a9c2e8d4cfd9..b4501647795ea24cae015cf5976ab219c084fffc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1035,6 +1035,9 @@ struct intel_gen6_power_mgmt {
        u8 rp0_freq;            /* Non-overclocked max frequency. */
        u32 cz_freq;
 
+       u8 up_threshold; /* Current %busy required to uplock */
+       u8 down_threshold; /* Current %busy required to downclock */
+
        int last_adj;
        enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 14ecb4d13a1aa2b24ca102097c90811bddc8c190..128a6f40b45093a0a67d7fef6ecf81038a8570a3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1049,7 +1049,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
        if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
                if (!vlv_c0_above(dev_priv,
                                  &dev_priv->rps.down_ei, &now,
-                                 VLV_RP_DOWN_EI_THRESHOLD))
+                                 dev_priv->rps.down_threshold))
                        events |= GEN6_PM_RP_DOWN_THRESHOLD;
                dev_priv->rps.down_ei = now;
        }
@@ -1057,7 +1057,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
        if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
                if (vlv_c0_above(dev_priv,
                                 &dev_priv->rps.up_ei, &now,
-                                VLV_RP_UP_EI_THRESHOLD))
+                                dev_priv->rps.up_threshold))
                        events |= GEN6_PM_RP_UP_THRESHOLD;
                dev_priv->rps.up_ei = now;
        }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b01da4ebcebe1779bbf052ae77d1f4e61534af05..77d8874c2fc37c643fd64bb2b9efc1b702fd5246 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -671,8 +671,6 @@ enum skl_disp_power_wells {
 #define   FB_FMAX_VMIN_FREQ_LO_MASK            0xf8000000
 
 #define VLV_CZ_CLOCK_TO_MILLI_SEC              100000
-#define VLV_RP_UP_EI_THRESHOLD                 90
-#define VLV_RP_DOWN_EI_THRESHOLD               70
 
 /* vlv2 north clock has */
 #define CCK_FUSE_REG                           0x8

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67e1e61c50e7d380ca985bc7ad2222e1c55f9c39..9c705dec853eff5ccd180e2aa69724c4fdd59b0b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3934,6 +3934,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
                    GEN6_RP_DOWN_IDLE_AVG);
 
        dev_priv->rps.power = new_power;
+       dev_priv->rps.up_threshold = threshold_up;
+       dev_priv->rps.down_threshold = threshold_down;
        dev_priv->rps.last_adj = 0;
 }
 
@@ -4005,8 +4007,11 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
                      "Odd GPU freq value\n"))
                val &= ~1;
 
-       if (val != dev_priv->rps.cur_freq)
+       if (val != dev_priv->rps.cur_freq) {
                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+               if (!IS_CHERRYVIEW(dev_priv))
+                       gen6_set_rps_thresholds(dev_priv, val);
+       }
 
        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
@@ -4055,6 +4060,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
                                & GENFREQSTATUS) == 0, 100))
                DRM_ERROR("timed out waiting for Punit\n");
 
+       gen6_set_rps_thresholds(dev_priv, val);
        vlv_force_gfx_clock(dev_priv, false);
 
        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));