drm/amdgpu: always flush the TLB on gfx8

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing")
Reviewed-by: Alex Deucher <[email protected]>
Tested-by: Michal Kubecek <[email protected]>
Signed-off-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 109d8dd71c116f443f7a91530469c2503db6b63c..dc76d2b3ce52fdcb9ba1623c6ab9499dbde9da2c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -793,6 +793,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
        flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
                     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+       /*
+        * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+        */
+       flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
        memset(&params, 0, sizeof(params));
        params.adev = adev;
        params.vm = vm;