- interrupts: The interrupt number to the cpu. The interrupt specifier format
depends on the interrupt controller.
-- -[PRELIMINARY: the dma channel allocation will change once there are
-- -official DMA bindings]
++ +- dmas : Two or more DMA channel specifiers following the convention outlined
++ + in bindings/dma/dma.txt
-- -- tx-dma-channel: The dma channel specifier for tx operations. The format of
-- - the dma specifier depends on the dma controller.
-- -
-- -- rx-dma-channel: The dma channel specifier for rx operations. The format of
-- - the dma specifier depends on the dma controller.
++ +- dma-names: Names for the dma channels. There must be at least one channel
++ + named "tx" for transmit and named "rx" for receive.
Required Board Specific Properties:
- num-cs: Specifies the number of chip select lines supported. If
not specified, the default number of chip select lines is set to 1.
+ ++- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
+ ++
SPI Controller specific data in SPI slave nodes:
- The spi slave nodes should provide the following information which is required
by the spi controller.
- -- - cs-gpio: A gpio specifier that specifies the gpio line used as
- -- the slave select line by the spi controller. The format of the gpio
- -- specifier depends on the gpio controller.
- --
- samsung,spi-feedback-delay: The sampling phase shift to be applied on the
miso line (to account for any lag in the miso line). The following are the
valid values.
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
interrupts = <0 66 0>;
-- - tx-dma-channel = <&pdma0 5>;
-- - rx-dma-channel = <&pdma0 4>;
++ + dmas = <&pdma0 5
++ + &pdma0 4>;
++ + dma-names = "tx", "rx";
++ + #address-cells = <1>;
++ + #size-cells = <0>;
};
- Board Specific Portion:
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
+ ++ cs-gpios = <&gpa2 5 0>;
w25q80bw@0 {
#address-cells = <1>;
spi-max-frequency = <10000>;
controller-data {
- -- cs-gpio = <&gpa2 5 1 0 3>;
samsung,spi-feedback-delay = <0>;
};