Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk...

 - Various DT of_node refcount fixes
 - Support for fixed rate clks populated from an MMIO register
 - Remove clps711x driver as the board support is gone

* clk-of-refcount:
  clk: dove: fix refcount leak in dove_clk_init()
  clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init()
  clk: armada-xp: fix refcount leak in axp_clk_init()
  clk: kirkwood: fix refcount leak in kirkwood_clk_init()
  clk: armada-370: fix refcount leak in a370_clk_init()
  clk: vf610: fix refcount leak in vf610_clocks_init()
  clk: imx7d: fix refcount leak in imx7d_clocks_init()
  clk: imx6sx: fix refcount leak in imx6sx_clocks_init()
  clk: imx6q: fix refcount leak in imx6q_clocks_init()
  clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()
  clk: socfpga: fix refcount leak
  clk: ti: fix refcount leak in ti_dt_clocks_register()
  clk: qoriq: fix refcount leak in clockgen_init()
  clk: highbank: fix refcount leak in hb_clk_init()

* clk-mmio-fixed-clock:
  clk: Add Fixed MMIO clock driver
  dt-bindings: clk: Add bindings for Fixed MMIO clock

* clk-remove-clps:
  clk: clps711x: Remove board support

* clk-socfpga-parent:
  clk: socfpga: Don't have get_parent for single parent ops

* clk-struct-size:
  clk: imx: imx7ulp: use struct_size() in kzalloc()

diff --combined drivers/clk/Kconfig
index d2f0bb5ba47eabd3702a9c249f51f81f8d25a318,81cdb4eaca07fe13322e24593123dc0936f6ece1,296972518db4d217e46856d6a703e878e732e4c4,e5b2fe80eab432c699242cd3146e5c97e2928f7a,81cdb4eaca07fe13322e24593123dc0936f6ece1,e5b2fe80eab432c699242cd3146e5c97e2928f7a..e705aab9e38ba8f6b82fc74ba74bbee5e3ec9843
--- 1/drivers/clk/Kconfig
--- 2/drivers/clk/Kconfig
--- 3/drivers/clk/Kconfig
--- 4/drivers/clk/Kconfig
--- 5/drivers/clk/Kconfig
--- 6/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@@@@@@ -283,18 -283,10 -283,25 -283,19 -283,10 -283,19 +283,24 @@@@@@@ config COMMON_CLK_STM32H
        ---help---
          Support for stm32h7 SoC family clocks
      
 +  + config COMMON_CLK_BD718XX
 +  +   tristate "Clock driver for ROHM BD718x7 PMIC"
 +  +   depends on MFD_ROHM_BD718XX
 +  +   help
 +  +     This driver supports ROHM BD71837 and ROHM BD71847
 +  +     PMICs clock gates.
 +  + 
++ +++config COMMON_CLK_FIXED_MMIO
++ +++  bool "Clock driver for Memory Mapped Fixed values"
++ +++  depends on COMMON_CLK && OF
++ +++  help
++ +++    Support for Memory Mapped IO Fixed clocks
++ +++
      source "drivers/clk/actions/Kconfig"
      source "drivers/clk/bcm/Kconfig"
      source "drivers/clk/hisilicon/Kconfig"
  -- -source "drivers/clk/imx/Kconfig"
      source "drivers/clk/imgtec/Kconfig"
 +  + source "drivers/clk/imx/Kconfig"
      source "drivers/clk/ingenic/Kconfig"
      source "drivers/clk/keystone/Kconfig"
      source "drivers/clk/mediatek/Kconfig"

diff --combined drivers/clk/clk-qoriq.c
index 5baa9e051110c3036570b884b6914dd6245b0233,97a0029a1cca2fb55ef3dc1236dacfc03b964653,5baa9e051110c3036570b884b6914dd6245b0233,5baa9e051110c3036570b884b6914dd6245b0233,4c30b6e799ed1ea1e22dcc8f920ec54309a024f6,5baa9e051110c3036570b884b6914dd6245b0233..0e84f6dfa54e85eb664bb8ca395e9cb8afd15327
--- 1/drivers/clk/clk-qoriq.c
--- 2/drivers/clk/clk-qoriq.c
--- 3/drivers/clk/clk-qoriq.c
--- 4/drivers/clk/clk-qoriq.c
--- 5/drivers/clk/clk-qoriq.c
--- 6/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@@@@@@ -1389,6 -1389,7 -1389,6 -1389,6 -1389,6 -1389,6 +1389,7 @@@@@@@ static void __init clockgen_init(struc
                                pr_err("%s: Couldn't map %pOF regs\n", __func__,
                                       guts);
                        }
+ ++++                  of_node_put(guts);
                }
      
        }
@@@@@@@ -1418,23 -1419,12 -1418,23 -1418,23 -1418,12 -1418,23 +1419,23 @@@@@@@ err
      
      CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
      CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
 +  + CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
      
      /* Legacy nodes */
      CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);

diff --combined drivers/clk/imx/clk-imx6q.c
index 716eac3136b4d712f5865476db52188bf11b6a85,53617e0632a9b75b67821a3822f73f6bbb21771a,716eac3136b4d712f5865476db52188bf11b6a85,716eac3136b4d712f5865476db52188bf11b6a85,bbe0c60f4d09f868a0a5c7d5cca22d72e66e0013,716eac3136b4d712f5865476db52188bf11b6a85..708e7c5590ddc89f01f691623748a731396fc26c
--- 1/drivers/clk/imx/clk-imx6q.c
--- 2/drivers/clk/imx/clk-imx6q.c
--- 3/drivers/clk/imx/clk-imx6q.c
--- 4/drivers/clk/imx/clk-imx6q.c
--- 5/drivers/clk/imx/clk-imx6q.c
--- 6/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@@@@@@ -225,41 -225,6 -225,41 -225,41 -225,6 -225,41 +225,41 @@@@@@@ static void of_assigned_ldb_sels(struc
        }
      }
      
 +  + static bool pll6_bypassed(struct device_node *node)
 +  + {
 +  +   int index, ret, num_clocks;
 +  +   struct of_phandle_args clkspec;
 +  + 
 +  +   num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
 +  +                                           "#clock-cells");
 +  +   if (num_clocks < 0)
 +  +           return false;
 +  + 
 +  +   for (index = 0; index < num_clocks; index++) {
 +  +           ret = of_parse_phandle_with_args(node, "assigned-clocks",
 +  +                                            "#clock-cells", index,
 +  +                                            &clkspec);
 +  +           if (ret < 0)
 +  +                   return false;
 +  + 
 +  +           if (clkspec.np == node &&
 +  +               clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
 +  +                   break;
 +  +   }
 +  + 
 +  +   /* PLL6 bypass is not part of the assigned clock list */
 +  +   if (index == num_clocks)
 +  +           return false;
 +  + 
 +  +   ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
 +  +                                    "#clock-cells", index, &clkspec);
 +  + 
 +  +   if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
 +  +           return true;
 +  + 
 +  +   return false;
 +  + }
 +  + 
      #define CCM_CCDR          0x04
      #define CCM_CCSR          0x0c
      #define CCM_CS2CDR                0x2c
@@@@@@@ -449,28 -414,17 -449,28 -449,28 -414,16 -449,28 +449,29 @@@@@@@ static void __init imx6q_clocks_init(st
        int ret;
      
        clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
 -  -   clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
 -  -   clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
 -  -   clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
 +  +   clk[IMX6QDL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
 +  +   if (IS_ERR(clk[IMX6QDL_CLK_CKIL]))
 +  +           clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
 +  +   clk[IMX6QDL_CLK_CKIH] = of_clk_get_by_name(ccm_node, "ckih1");
 +  +   if (IS_ERR(clk[IMX6QDL_CLK_CKIH]))
 +  +           clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
 +  +   clk[IMX6QDL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
 +  +   if (IS_ERR(clk[IMX6QDL_CLK_OSC]))
 +  +           clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
 +  + 
        /* Clock source from external clock via CLK1/2 PADs */
 -  -   clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
 -  -   clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
 +  +   clk[IMX6QDL_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1");
 +  +   if (IS_ERR(clk[IMX6QDL_CLK_ANACLK1]))
 +  +           clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
 +  + 
 +  +   clk[IMX6QDL_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2");
 +  +   if (IS_ERR(clk[IMX6QDL_CLK_ANACLK2]))
 +  +           clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
      
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
        anatop_base = base = of_iomap(np, 0);
        WARN_ON(!base);
+ ++++  of_node_put(np);
      
        /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
        if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
@@@@@@@ -538,32 -492,16 -538,32 -538,32 -491,16 -538,32 +539,32 @@@@@@@
        clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
        clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
      
 -  -   clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
 -  -   clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 +  +   /*
 +  +    * The ENET PLL is special in that is has multiple outputs with
 +  +    * different post-dividers that are all affected by the single bypass
 +  +    * bit, so a single mux bit affects 3 independent branches of the clock
 +  +    * tree. There is no good way to model this in the clock framework and
 +  +    * dynamically changing the bypass bit, will yield unexpected results.
 +  +    * So we treat any configuration that bypasses the ENET PLL as
 +  +    * essentially static with the divider ratios reflecting the bypass
 +  +    * status.
 +  +    *
 +  +    */
 +  +   if (!pll6_bypassed(ccm_node)) {
 +  +           clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
 +  +           clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
 +  +           clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
 +  +                                           base + 0xe0, 0, 2, 0, clk_enet_ref_table,
 +  +                                           &imx_ccm_lock);
 +  +   } else {
 +  +           clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 1);
 +  +           clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
 +  +           clk[IMX6QDL_CLK_ENET_REF] = imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1);
 +  +   }
      
        clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
        clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
      
 -  -   clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
 -  -                   base + 0xe0, 0, 2, 0, clk_enet_ref_table,
 -  -                   &imx_ccm_lock);
 -  - 
        clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
        clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
      
@@@@@@@ -571,12 -509,8 -571,12 -571,12 -508,8 -571,12 +572,12 @@@@@@@
         * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
         * independently configured as clock inputs or outputs.  We treat
         * the "output_enable" bit as a gate, even though it's really just
 -  -    * enabling clock output.
 +  +    * enabling clock output. Initially the gate bits are cleared, as
 +  +    * otherwise the exclusive configuration gets locked in the setup done
 +  +    * by software running before the clock driver, with no way to change
 +  +    * it.
         */
 +  +   writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
        clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
        clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
      
@@@@@@@ -804,8 -738,6 -804,8 -804,8 -737,6 -804,8 +805,8 @@@@@@@
        clk[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
        clk[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
        clk[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
 +  +   clk[IMX6QDL_CLK_DCIC1]        = imx_clk_gate2("dcic1",         "ipu1_podf",         base + 0x68, 24);
 +  +   clk[IMX6QDL_CLK_DCIC2]        = imx_clk_gate2("dcic2",         "ipu2_podf",         base + 0x68, 26);
        clk[IMX6QDL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
        clk[IMX6QDL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
        clk[IMX6QDL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);

diff --combined drivers/clk/imx/clk-imx7d.c
index 06c105d580a45e75390e7ac87eb7b2641a6f5027,12e2e85bbe1c305198bf7ab79684a78e19b0e18d,06c105d580a45e75390e7ac87eb7b2641a6f5027,06c105d580a45e75390e7ac87eb7b2641a6f5027,adb08f64c6918f040f3f9ef1e074fd4ba28da77f,06c105d580a45e75390e7ac87eb7b2641a6f5027..cfbd8d4edb8599b9cddbaec02f1a2832faa02bf7
--- 1/drivers/clk/imx/clk-imx7d.c
--- 2/drivers/clk/imx/clk-imx7d.c
--- 3/drivers/clk/imx/clk-imx7d.c
--- 4/drivers/clk/imx/clk-imx7d.c
--- 5/drivers/clk/imx/clk-imx7d.c
--- 6/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@@@@@@ -404,6 -404,7 -404,6 -404,6 -404,6 -404,6 +404,7 @@@@@@@ static void __init imx7d_clocks_init(st
        np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
        base = of_iomap(np, 0);
        WARN_ON(!base);
+ ++++  of_node_put(np);
      
        clks[IMX7D_PLL_ARM_MAIN_SRC]  = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
        clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
@@@@@@@ -886,6 -887,9 -886,6 -886,6 -886,9 -886,6 +887,6 @@@@@@@
        /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
        clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
      
 -  -   /* set uart module clock's parent clock source that must be great then 80MHz */
 -  -   clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 -  - 
        /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
        clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
        clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);