By default the SGTL5000 derives bit and frame clock from MCLK, which
does not produce particularly accurate results. The SGTL5000 PLL does
improve the accuracy, but also increases power consumption. Using the
SoC SAI interface as bit and frame clock source results in the best
accuracy without the power consumption increase downside. Switch the
bit and frame clock direction from SAI to SGTL5000, reduce mclk-fs to
match.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
sgtl5000_tx_endpoint: endpoint@0 {
reg = <0>;
- bitclock-master;
- frame-master;
remote-endpoint = <&sai2a_endpoint>;
};
sgtl5000_rx_endpoint: endpoint@1 {
reg = <1>;
- bitclock-master;
- frame-master;
remote-endpoint = <&sai2b_endpoint>;
};
};
sai2a_port: port {
sai2a_endpoint: endpoint {
remote-endpoint = <&sgtl5000_tx_endpoint>;
+ bitclock-master;
dai-format = "i2s";
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
- mclk-fs = <512>;
+ frame-master;
+ mclk-fs = <256>;
};
};
};
sai2b_port: port {
sai2b_endpoint: endpoint {
remote-endpoint = <&sgtl5000_rx_endpoint>;
+ bitclock-master;
dai-format = "i2s";
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
- mclk-fs = <512>;
+ frame-master;
+ mclk-fs = <256>;
};
};
};