ata: ahci: Drop low power policy board type

The low power policy board type was introduced to allow systems
to get into deep states reliably.  Before it was introduced `min_power`
was causing problems for a number of drives.  New power policies
`min_power_with_partial` and `med_power_with_dipm` have been introduced
which provide a more stable baseline for systems.

Tested-by: Damien Le Moal <[email protected]>
Tested-by: Jian-Hong Pan <[email protected]>
Acked-by: Jian-Hong Pan <[email protected]>
Acked-by: Christoph Hellwig <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
Reviewed-by: Mario Limonciello <[email protected]>
Reviewed-by: Mika Westerberg <[email protected]>
Suggested-by: Christoph Hellwig <[email protected]>
Signed-off-by: Mario Limonciello <[email protected]>
[cassel: rebase patch and fix trivial conflicts]
Signed-off-by: Niklas Cassel <[email protected]>

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 42b51c9812a0ebab52d2dfd4cb94e563c8312f17..928ec93c6b45c34831196b38ebbd6d7550113ab3 100644 (file)
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -116,15 +116,14 @@ config SATA_AHCI
          If unsure, say N.
 
 config SATA_MOBILE_LPM_POLICY
-       int "Default SATA Link Power Management policy for low power chipsets"
+       int "Default SATA Link Power Management policy"
        range 0 4
        default 0
        depends on SATA_AHCI
        help
          Select the Default SATA Link Power Management (LPM) policy to use
          for chipsets / "South Bridges" supporting low-power modes. Such
-         chipsets are typically found on most laptops but desktops and
-         servers now also widely use chipsets supporting low power modes.
+         chipsets are ubiquitous across laptops, desktops and servers.
 
          The value set has the following meanings:
                0 => Keep firmware settings

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9d052ff2b86c5f6aedbb88decaa8ed057fb107c8..ae0a592e21851aa4566261e11b5c264ce28992f8 100644 (file)
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -50,7 +50,6 @@ enum board_ids {
        board_ahci,
        board_ahci_43bit_dma,
        board_ahci_ign_iferr,
-       board_ahci_low_power,
        board_ahci_no_debounce_delay,
        board_ahci_nomsi,
        board_ahci_noncq,
@@ -143,13 +142,6 @@ static const struct ata_port_info ahci_port_info[] = {
                .udma_mask      = ATA_UDMA6,
                .port_ops       = &ahci_ops,
        },
-       [board_ahci_low_power] = {
-               AHCI_HFLAGS     (AHCI_HFLAG_USE_LPM_POLICY),
-               .flags          = AHCI_FLAG_COMMON,
-               .pio_mask       = ATA_PIO4,
-               .udma_mask      = ATA_UDMA6,
-               .port_ops       = &ahci_ops,
-       },
        [board_ahci_no_debounce_delay] = {
                .flags          = AHCI_FLAG_COMMON,
                .link_flags     = ATA_LFLAG_NO_DEBOUNCE_DELAY,
@@ -283,13 +275,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
        { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
        { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
-       { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
-       { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
-       { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
-       { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
-       { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
        { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
-       { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
+       { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
        { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
        { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
        { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
@@ -299,9 +291,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
        { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
        { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
-       { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
+       { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
        { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
-       { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
+       { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
        { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
        { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
        { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
@@ -324,9 +316,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
        { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
        { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
-       { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
+       { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
        { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
-       { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
+       { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
        { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
        { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
        { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
@@ -334,29 +326,29 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
        { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
        { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
-       { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
+       { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther M AHCI */
        { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
        { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
        { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
-       { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
+       { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther M RAID */
        { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
        { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
-       { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
+       { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx M AHCI */
        { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
-       { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
+       { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx M RAID */
        { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
-       { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
+       { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx M RAID */
        { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
-       { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
-       { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
-       { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
-       { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx M RAID */
+       { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci }, /* Cannon Lake PCH-LP AHCI */
        { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
        { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
        { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
@@ -390,26 +382,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
        { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
        { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
-       { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
-       { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat LP RAID */
        { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
-       { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
+       { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
        { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
-       { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
+       { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
        { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
-       { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
+       { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
        { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
-       { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
-       { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
-       { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
-       { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
+       { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
+       { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise LP RAID */
+       { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise LP RAID */
        { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
-       { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
+       { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise M AHCI */
        { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
        { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
-       { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
+       { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise M RAID */
        { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
        { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
        { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
@@ -422,16 +414,16 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
        { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
        { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
-       { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
-       { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
-       { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
-       { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
-       { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
-       { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
-       { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
+       { PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
+       { PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
+       { PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Tr. AHCI */
+       { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* ApolloLake AHCI */
+       { PCI_VDEVICE(INTEL, 0x34d3), board_ahci }, /* Ice Lake LP AHCI */
+       { PCI_VDEVICE(INTEL, 0x02d3), board_ahci }, /* Comet Lake PCH-U AHCI */
+       { PCI_VDEVICE(INTEL, 0x02d7), board_ahci }, /* Comet Lake PCH RAID */
        /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
-       { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
-       { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */
+       { PCI_VDEVICE(INTEL, 0x4b63), board_ahci }, /* Elkhart Lake AHCI */
+       { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci }, /* Alder Lake-P AHCI */
 
        /* JMicron 360/1/3/5/6, match class to avoid IDE function */
        { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -459,7 +451,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
        { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
        { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
        { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
-       { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
+       { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
        /* AMD is using RAID class only for ahci controllers */
        { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
          PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
@@ -1660,11 +1652,6 @@ static void ahci_update_initial_lpm_policy(struct ata_port *ap)
        struct ahci_host_priv *hpriv = ap->host->private_data;
        int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
 
-
-       /* Ignore processing for chipsets that don't use policy */
-       if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
-               return;
-
        /*
         * AHCI contains a known incompatibility between LPM and hot-plug
         * removal events, see 7.3.1 Hot Plug Removal Detection and Power

diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index df8f8a1a3a34c3ee26d0d2b899522a82d220b6c2..4a0a602c6b16bf24c5bc70abf9b956b969da9706 100644 (file)
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -241,13 +241,10 @@ enum {
        AHCI_HFLAG_YES_ALPM             = BIT(23), /* force ALPM cap on */
        AHCI_HFLAG_NO_WRITE_TO_RO       = BIT(24), /* don't write to read
                                                      only registers */
-       AHCI_HFLAG_USE_LPM_POLICY       = BIT(25), /* chipset that should use
-                                                     SATA_MOBILE_LPM_POLICY
-                                                     as default lpm_policy */
-       AHCI_HFLAG_SUSPEND_PHYS         = BIT(26), /* handle PHYs during
+       AHCI_HFLAG_SUSPEND_PHYS         = BIT(25), /* handle PHYs during
                                                      suspend/resume */
-       AHCI_HFLAG_NO_SXS               = BIT(28), /* SXS not supported */
-       AHCI_HFLAG_43BIT_ONLY           = BIT(29), /* 43bit DMA addr limit */
+       AHCI_HFLAG_NO_SXS               = BIT(26), /* SXS not supported */
+       AHCI_HFLAG_43BIT_ONLY           = BIT(27), /* 43bit DMA addr limit */
 
        /* ap->flags bits */