Merge branch 'x86/urgent' into x86/mm to pick up dependencies

diff --combined arch/x86/entry/entry_64.S
index 8a78030a82f258ee42da722fb227c60928bb8534,805f52703ee3377f88180eb3467a34bf2bc40e87..74180b3d43bd74594d00a738e77b03e20d2a3c99
--- 1/arch/x86/entry/entry_64.S
--- 2/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@@ -55,7 -55,7 +55,7 @@@ END(native_usergs_sysret64
  
  .macro TRACE_IRQS_FLAGS flags:req
  #ifdef CONFIG_TRACE_IRQFLAGS
-       bt      $9, \flags              /* interrupts off? */
+       btl     $9, \flags              /* interrupts off? */
        jnc     1f
        TRACE_IRQS_ON
  1:
@@@ -260,13 -260,8 +260,13 @@@ GLOBAL(entry_SYSCALL_64_after_hwframe
         * Change top bits to match most significant bit (47th or 56th bit
         * depending on paging mode) in the address.
         */
 +#ifdef CONFIG_X86_5LEVEL
 +      ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
 +              "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
 +#else
        shl     $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
        sar     $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
 +#endif
  
        /* If this changed %rcx, it was not canonical */
        cmpq    %rcx, %r11

diff --combined arch/x86/kernel/cpu/mcheck/mce.c
index 3d8c573a9a27619fd336fc06da536885665ebb61,466f47301334ba0c8e64c17fd8fa5b7903cca44f..6d43f18e39eaaf758b6642a6dbe40912c40fd083
--- 1/arch/x86/kernel/cpu/mcheck/mce.c
--- 2/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@@ -56,6 -56,9 +56,9 @@@
  
  static DEFINE_MUTEX(mce_log_mutex);
  
+ /* sysfs synchronization */
+ static DEFINE_MUTEX(mce_sysfs_mutex);
+ 
  #define CREATE_TRACE_POINTS
  #include <trace/events/mce.h>
  
@@@ -130,6 -133,8 +133,8 @@@ void mce_setup(struct mce *m
  
        if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
                rdmsrl(MSR_PPIN, m->ppin);
+ 
+       m->microcode = boot_cpu_data.microcode;
  }
  
  DEFINE_PER_CPU(struct mce, injectm);
@@@ -262,7 -267,7 +267,7 @@@ static void __print_mce(struct mce *m
         */
        pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
                m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
-               cpu_data(m->extcpu).microcode);
+               m->microcode);
  }
  
  static void print_mce(struct mce *m)
@@@ -1088,7 -1093,19 +1093,7 @@@ static void mce_unmap_kpfn(unsigned lon
         * a legal address.
         */
  
 -/*
 - * Build time check to see if we have a spare virtual bit. Don't want
 - * to leave this until run time because most developers don't have a
 - * system that can exercise this code path. This will only become a
 - * problem if/when we move beyond 5-level page tables.
 - *
 - * Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD)
 - */
 -#if PGDIR_SHIFT + 9 < 63
        decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
 -#else
 -#error "no unused virtual bit available"
 -#endif
  
        if (set_memory_np(decoy_addr, 1))
                pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
@@@ -2074,6 -2091,7 +2079,7 @@@ static ssize_t set_ignore_ce(struct dev
        if (kstrtou64(buf, 0, &new) < 0)
                return -EINVAL;
  
+       mutex_lock(&mce_sysfs_mutex);
        if (mca_cfg.ignore_ce ^ !!new) {
                if (new) {
                        /* disable ce features */
@@@ -2086,6 -2104,8 +2092,8 @@@
                        on_each_cpu(mce_enable_ce, (void *)1, 1);
                }
        }
+       mutex_unlock(&mce_sysfs_mutex);
+ 
        return size;
  }
  
@@@ -2098,6 -2118,7 +2106,7 @@@ static ssize_t set_cmci_disabled(struc
        if (kstrtou64(buf, 0, &new) < 0)
                return -EINVAL;
  
+       mutex_lock(&mce_sysfs_mutex);
        if (mca_cfg.cmci_disabled ^ !!new) {
                if (new) {
                        /* disable cmci */
@@@ -2109,6 -2130,8 +2118,8 @@@
                        on_each_cpu(mce_enable_ce, NULL, 1);
                }
        }
+       mutex_unlock(&mce_sysfs_mutex);
+ 
        return size;
  }
  
@@@ -2116,8 -2139,19 +2127,19 @@@ static ssize_t store_int_with_restart(s
                                      struct device_attribute *attr,
                                      const char *buf, size_t size)
  {
-       ssize_t ret = device_store_int(s, attr, buf, size);
+       unsigned long old_check_interval = check_interval;
+       ssize_t ret = device_store_ulong(s, attr, buf, size);
+ 
+       if (check_interval == old_check_interval)
+               return ret;
+ 
+       if (check_interval < 1)
+               check_interval = 1;
+ 
+       mutex_lock(&mce_sysfs_mutex);
        mce_restart();
+       mutex_unlock(&mce_sysfs_mutex);
+ 
        return ret;
  }
  
@@@ -2321,12 -2355,6 +2343,12 @@@ static __init int mcheck_init_device(vo
  {
        int err;
  
 +      /*
 +       * Check if we have a spare virtual bit. This will only become
 +       * a problem if/when we move beyond 5-level page tables.
 +       */
 +      MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
 +
        if (!mce_available(&boot_cpu_data)) {
                err = -EIO;
                goto err_out;

diff --combined arch/x86/mm/fault.c
index e6af2b464c3d0781334e751d9eb8bfb295610612,25a30b5d6582f2cd7937ed1beb51de989db24280..84d702a71afe85c5130fff09b9325e7ce91c215b
--- 1/arch/x86/mm/fault.c
--- 2/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@@ -330,7 -330,7 +330,7 @@@ static noinline int vmalloc_fault(unsig
        if (!pmd_k)
                return -1;
  
-       if (pmd_huge(*pmd_k))
+       if (pmd_large(*pmd_k))
                return 0;
  
        pte_k = pte_offset_kernel(pmd_k, address);
@@@ -439,7 -439,7 +439,7 @@@ static noinline int vmalloc_fault(unsig
        if (pgd_none(*pgd_ref))
                return -1;
  
 -      if (CONFIG_PGTABLE_LEVELS > 4) {
 +      if (pgtable_l5_enabled) {
                if (pgd_none(*pgd)) {
                        set_pgd(pgd, *pgd_ref);
                        arch_flush_lazy_mmu_mode();
@@@ -454,7 -454,7 +454,7 @@@
        if (p4d_none(*p4d_ref))
                return -1;
  
 -      if (p4d_none(*p4d) && CONFIG_PGTABLE_LEVELS == 4) {
 +      if (p4d_none(*p4d) && !pgtable_l5_enabled) {
                set_p4d(p4d, *p4d_ref);
                arch_flush_lazy_mmu_mode();
        } else {
@@@ -475,7 -475,7 +475,7 @@@
        if (pud_none(*pud) || pud_pfn(*pud) != pud_pfn(*pud_ref))
                BUG();
  
-       if (pud_huge(*pud))
+       if (pud_large(*pud))
                return 0;
  
        pmd = pmd_offset(pud, address);
@@@ -486,7 -486,7 +486,7 @@@
        if (pmd_none(*pmd) || pmd_pfn(*pmd) != pmd_pfn(*pmd_ref))
                BUG();
  
-       if (pmd_huge(*pmd))
+       if (pmd_large(*pmd))
                return 0;
  
        pte_ref = pte_offset_kernel(pmd_ref, address);

diff --combined arch/x86/platform/intel-mid/intel-mid.c
index c556f1e8936e5791846b8a251e2516ecdfe91cbd,fb1df9488e98b843f89155b3afbfe5958128a306..2ebdf31d999637b5649abc2371302f9aa92a8eac
--- 1/arch/x86/platform/intel-mid/intel-mid.c
--- 2/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@@ -79,7 -79,7 +79,7 @@@ static void intel_mid_power_off(void
  
  static void intel_mid_reboot(void)
  {
-       intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
+       intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
  }
  
  static unsigned long __init intel_mid_calibrate_tsc(void)
@@@ -199,12 -199,6 +199,12 @@@ void __init x86_intel_mid_early_setup(v
  
        legacy_pic = &null_legacy_pic;
  
 +      /*
 +       * Do nothing for now as everything needed done in
 +       * x86_intel_mid_early_setup() below.
 +       */
 +      x86_init.acpi.reduced_hw_early_init = x86_init_noop;
 +
        pm_power_off = intel_mid_power_off;
        machine_ops.emergency_restart  = intel_mid_reboot;