gcc-plugins: Automate make rule generation

There's no reason to repeat the same names in the Makefile when the .so
files have already been listed. The .o list can be generated from them.

Reported-by: PaX Team <[email protected]>
Signed-off-by: Emese Revfy <[email protected]>
[kees: clarified commit message]
Signed-off-by: Kees Cook <[email protected]>

diff --git a/scripts/gcc-plugins/Makefile b/scripts/gcc-plugins/Makefile
index 88c8ec47232b1c8595992109fbdd8a503cc6cc09..ee0a75d2a1c703a2589eccebbabe4bde7f439b8d 100644 (file)
--- a/scripts/gcc-plugins/Makefile
+++ b/scripts/gcc-plugins/Makefile
@@ -21,7 +21,6 @@ endif
 $(HOSTLIBS)-y := $(GCC_PLUGIN)
 always := $($(HOSTLIBS)-y)
 
-cyc_complexity_plugin-objs := cyc_complexity_plugin.o
-sancov_plugin-objs := sancov_plugin.o
+$(foreach p,$($(HOSTLIBS)-y:%.so=%),$(eval $(p)-objs := $(p).o))
 
 clean-files += *.so