Merge tag 'bcm2835-dt-fixes-2017-05-16' into devicetree/fixes

This pull request brings in a fix for booting on SMP Raspberry Pis,
particularly with maxcpus=1

Signed-off-by: Florian Fainelli <[email protected]>

diff --combined arch/arm/boot/dts/bcm283x.dtsi
index 561f27d8d92224fe8f4f8c3224a5441f2d41175a,1ac7c0dc65771499a37e823ab1b71181304fb400..9444a9a9ba1057e6b594dc8e2595ac1e5ec593fb
--- 1/arch/arm/boot/dts/bcm283x.dtsi
--- 2/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@@ -3,6 -3,11 +3,11 @@@
  #include <dt-bindings/clock/bcm2835-aux.h>
  #include <dt-bindings/gpio/gpio.h>
  
+ /* firmware-provided startup stubs live here, where the secondary CPUs are
+  * spinning.
+  */
+ /memreserve/ 0x00000000 0x00001000;
+ 
  /* This include file covers the common peripherals and configuration between
   * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
   * bcm2835.dtsi and bcm2836.dtsi.
@@@ -198,8 -203,8 +203,8 @@@
                                brcm,pins = <0 1>;
                                brcm,function = <BCM2835_FSEL_ALT0>;
                        };
 -                      i2c0_gpio32: i2c0_gpio32 {
 -                              brcm,pins = <32 34>;
 +                      i2c0_gpio28: i2c0_gpio28 {
 +                              brcm,pins = <28 29>;
                                brcm,function = <BCM2835_FSEL_ALT0>;
                        };
                        i2c0_gpio44: i2c0_gpio44 {
@@@ -295,28 -300,20 +300,28 @@@
                        /* Separate from the uart0_gpio14 group
                         * because it conflicts with spi1_gpio16, and
                         * people often run uart0 on the two pins
 -                       * without flow contrl.
 +                       * without flow control.
                         */
                        uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
                                brcm,pins = <16 17>;
                                brcm,function = <BCM2835_FSEL_ALT3>;
                        };
 -                      uart0_gpio30: uart0_gpio30 {
 +                      uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
                                brcm,pins = <30 31>;
                                brcm,function = <BCM2835_FSEL_ALT3>;
                        };
 -                      uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
 +                      uart0_gpio32: uart0_gpio32 {
                                brcm,pins = <32 33>;
                                brcm,function = <BCM2835_FSEL_ALT3>;
                        };
 +                      uart0_gpio36: uart0_gpio36 {
 +                              brcm,pins = <36 37>;
 +                              brcm,function = <BCM2835_FSEL_ALT2>;
 +                      };
 +                      uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 +                              brcm,pins = <38 39>;
 +                              brcm,function = <BCM2835_FSEL_ALT2>;
 +                      };
  
                        uart1_gpio14: uart1_gpio14 {
                                brcm,pins = <14 15>;
@@@ -334,6 -331,10 +339,6 @@@
                                brcm,pins = <30 31>;
                                brcm,function = <BCM2835_FSEL_ALT5>;
                        };
 -                      uart1_gpio36: uart1_gpio36 {
 -                              brcm,pins = <36 37 38 39>;
 -                              brcm,function = <BCM2835_FSEL_ALT2>;
 -                      };
                        uart1_gpio40: uart1_gpio40 {
                                brcm,pins = <40 41>;
                                brcm,function = <BCM2835_FSEL_ALT5>;