Merge patch series "RISC-V: Test th.sxstatus.MAEE bit before enabling MAEE"

Christoph Müllner <[email protected]> says:

Currently, the Linux kernel suffers from a boot regression when running
on the c906 QEMU emulation. Details have been reported here by Björn Töpel:
  https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg04766.html

The main issue is, that Linux enables XTheadMae for CPUs that have a T-Head
mvendorid but QEMU maintainers don't want to emulate a CPU that uses
reserved bits in PTEs. See also the following discussion for more
context:
  https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

This series renames "T-Head PBMT" to "MAE"/"XTheadMae" and only enables
it if the th.sxstatus.MAEE bit is set.

The th.sxstatus CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

XTheadMae is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmae.adoc

The QEMU patch to emulate th.sxstatus with the MAEE bit not set is here:
  https://lore.kernel.org/all/20240329120427[email protected]/

After applying the referenced QEMU patch, this patchset allows to
successfully boot a C906 QEMU system emulation ("-cpu thead-c906").

* b4-shazam-lts:
  riscv: T-Head: Test availability bit before enabling MAE errata
  riscv: thead: Rename T-Head PBMT to MAE

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

diff --combined arch/riscv/include/asm/errata_list.h
index 1f2dbfb8a8bfc8c9f5d46b9129c26756941c4918,9bad9dfa2f7a167a6f1066de2ad2f4b4d8419d78..efd851e1b48321e1f098008ce8fe7755ab49339d
--- 1/arch/riscv/include/asm/errata_list.h
--- 2/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@@ -12,8 -12,8 +12,8 @@@
  #include <asm/vendorid_list.h>
  
  #ifdef CONFIG_ERRATA_ANDES
 -#define ERRATA_ANDESTECH_NO_IOCP      0
 -#define ERRATA_ANDESTECH_NUMBER               1
 +#define ERRATA_ANDES_NO_IOCP 0
 +#define ERRATA_ANDES_NUMBER 1
  #endif
  
  #ifdef CONFIG_ERRATA_SIFIVE
@@@ -23,7 -23,7 +23,7 @@@
  #endif
  
  #ifdef CONFIG_ERRATA_THEAD
- #define       ERRATA_THEAD_PBMT 0
+ #define       ERRATA_THEAD_MAE 0
  #define       ERRATA_THEAD_PMU 1
  #define       ERRATA_THEAD_NUMBER 2
  #endif
@@@ -53,20 -53,20 +53,20 @@@ asm(ALTERNATIVE("sfence.vma %0", "sfenc
   * in the default case.
   */
  #define ALT_SVPBMT_SHIFT 61
- #define ALT_THEAD_PBMT_SHIFT 59
+ #define ALT_THEAD_MAE_SHIFT 59
  #define ALT_SVPBMT(_val, prot)                                                \
  asm(ALTERNATIVE_2("li %0, 0\t\nnop",                                  \
                  "li %0, %1\t\nslli %0,%0,%3", 0,                      \
                        RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,  \
                  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,        \
-                       ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)    \
+                       ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)      \
                : "=r"(_val)                                            \
                : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),               \
-                 "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),            \
+                 "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT),             \
                  "I"(ALT_SVPBMT_SHIFT),                                \
-                 "I"(ALT_THEAD_PBMT_SHIFT))
+                 "I"(ALT_THEAD_MAE_SHIFT))
  
- #ifdef CONFIG_ERRATA_THEAD_PBMT
+ #ifdef CONFIG_ERRATA_THEAD_MAE
  /*
   * IO/NOCACHE memory types are handled together with svpbmt,
   * so on T-Head chips, check if no other memory type is set,
@@@ -83,11 -83,11 +83,11 @@@ asm volatile(ALTERNATIVE(                                          
        "slli    t3, t3, %3\n\t"                                        \
        "or      %0, %0, t3\n\t"                                        \
        "2:",  THEAD_VENDOR_ID,                                         \
-               ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)            \
+               ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE)              \
        : "+r"(_val)                                                    \
-       : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),              \
-         "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),                 \
-         "I"(ALT_THEAD_PBMT_SHIFT)                                     \
+       : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT),               \
+         "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT),                  \
+         "I"(ALT_THEAD_MAE_SHIFT)                                      \
        : "t3")
  #else
  #define ALT_THEAD_PMA(_val)
@@@ -112,6 -112,15 +112,6 @@@ asm volatile(ALTERNATIVE(                                         
  #define THEAD_C9XX_RV_IRQ_PMU                 17
  #define THEAD_C9XX_CSR_SCOUNTEROF             0x5c5
  
 -#define ALT_SBI_PMU_OVERFLOW(__ovl)                                   \
 -asm volatile(ALTERNATIVE(                                             \
 -      "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
 -      "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
 -              THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
 -              CONFIG_ERRATA_THEAD_PMU)                                \
 -      : "=r" (__ovl) :                                                \
 -      : "memory")
 -
  #endif /* __ASSEMBLY__ */
  
  #endif