]> Git Repo - linux.git/commitdiff
wcn36xx: Check DXE IRQ reason
authorRamon Fried <[email protected]>
Sun, 11 Mar 2018 12:01:43 +0000 (14:01 +0200)
committerKalle Valo <[email protected]>
Mon, 26 Mar 2018 15:27:27 +0000 (18:27 +0300)
IRQ reason was not cheked for errors.
Although error handing is not currently supported, it
will be nice to output an error value to the log if the
DMA operation failed.

Signed-off-by: Ramon Fried <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
drivers/net/wireless/ath/wcn36xx/dxe.c
drivers/net/wireless/ath/wcn36xx/dxe.h

index 8e4d6d9ea277309c8a23b7f4849b9520f60bf8a4..7d5ecaf02288793a4ffb25dd5ccff5f38bf910aa 100644 (file)
@@ -415,14 +415,31 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
                                          WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H,
                                          &int_reason);
 
-               /* TODO: Check int_reason */
-
                wcn36xx_dxe_write_register(wcn,
                                           WCN36XX_DXE_0_INT_CLR,
                                           WCN36XX_INT_MASK_CHAN_TX_H);
 
-               wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
-                                          WCN36XX_INT_MASK_CHAN_TX_H);
+               if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_ERR_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_H);
+
+                       wcn36xx_err("DXE IRQ reported error: 0x%x in high TX channel\n",
+                                       int_src);
+               }
+
+               if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_DONE_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_H);
+               }
+
+               if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_ED_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_H);
+               }
+
                wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n");
                reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
        }
@@ -431,14 +448,33 @@ static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
                wcn36xx_dxe_read_register(wcn,
                                          WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L,
                                          &int_reason);
-               /* TODO: Check int_reason */
 
                wcn36xx_dxe_write_register(wcn,
                                           WCN36XX_DXE_0_INT_CLR,
                                           WCN36XX_INT_MASK_CHAN_TX_L);
 
-               wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
-                                          WCN36XX_INT_MASK_CHAN_TX_L);
+
+               if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_ERR_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_L);
+
+                       wcn36xx_err("DXE IRQ reported error: 0x%x in low TX channel\n",
+                                       int_src);
+               }
+
+               if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_DONE_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_L);
+               }
+
+               if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) {
+                       wcn36xx_dxe_write_register(wcn,
+                                                  WCN36XX_DXE_0_INT_ED_CLR,
+                                                  WCN36XX_INT_MASK_CHAN_TX_L);
+               }
+
                wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n");
                reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
        }
index feb3cb7ee81fb82d58d0c66cf90b05a4c974b3e5..2bc376c5391b249c41f0da4b9bcf06211c430833 100644 (file)
@@ -262,6 +262,10 @@ H2H_TEST_RX_TX = DMA2
 #define WCN36XX_DXE_0_INT_DONE_CLR             (WCN36XX_DXE_MEM_REG + 0x38)
 #define WCN36XX_DXE_0_INT_ERR_CLR              (WCN36XX_DXE_MEM_REG + 0x3C)
 
+#define WCN36XX_CH_STAT_INT_DONE_MASK   0x00008000
+#define WCN36XX_CH_STAT_INT_ERR_MASK    0x00004000
+#define WCN36XX_CH_STAT_INT_ED_MASK     0x00002000
+
 #define WCN36XX_DXE_0_CH0_STATUS               (WCN36XX_DXE_MEM_REG + 0x404)
 #define WCN36XX_DXE_0_CH1_STATUS               (WCN36XX_DXE_MEM_REG + 0x444)
 #define WCN36XX_DXE_0_CH2_STATUS               (WCN36XX_DXE_MEM_REG + 0x484)
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