Merge tag 'x86_cache_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 cache resource control updates from Borislav Petkov:

 - Misc cleanups to the resctrl code in preparation for the ARM side
   (James Morse)

 - Add support for controlling per-thread memory bandwidth throttling
   delay values on hw which supports it (Fenghua Yu)

* tag 'x86_cache_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/resctrl: Enable user to view thread or core throttling mode
  x86/resctrl: Enumerate per-thread MBA controls
  cacheinfo: Move resctrl's get_cache_id() to the cacheinfo header file
  x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps
  x86/resctrl: Merge AMD/Intel parse_bw() calls
  x86/resctrl: Add struct rdt_membw::arch_needs_linear to explain AMD/Intel MBA difference
  x86/resctrl: Use is_closid_match() in more places
  x86/resctrl: Include pid.h
  x86/resctrl: Use container_of() in delayed_work handlers
  x86/resctrl: Fix stale comment
  x86/resctrl: Remove struct rdt_membw::max_delay
  x86/resctrl: Remove unused struct mbm_state::chunks_bw

diff --combined arch/x86/include/asm/cpufeatures.h
index a48458b04e1eab481e2421873681e657ab53d668,4a7473ae55ac95610d5a414b10c8a2285d7a5101..7b0afd5e6c57adb98ed06ffa9add159f1c716c6b
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -96,7 -96,7 +96,7 @@@
  #define X86_FEATURE_SYSCALL32         ( 3*32+14) /* "" syscall in IA32 userspace */
  #define X86_FEATURE_SYSENTER32                ( 3*32+15) /* "" sysenter in IA32 userspace */
  #define X86_FEATURE_REP_GOOD          ( 3*32+16) /* REP microcode works well */
 -/* free                                       ( 3*32+17) */
 +#define X86_FEATURE_SME_COHERENT      ( 3*32+17) /* "" AMD hardware-enforced cache coherency */
  #define X86_FEATURE_LFENCE_RDTSC      ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
  #define X86_FEATURE_ACC_POWER         ( 3*32+19) /* AMD Accumulated Power Mechanism */
  #define X86_FEATURE_NOPL              ( 3*32+20) /* The NOPL (0F 1F) instructions */
@@@ -288,6 -288,7 +288,7 @@@
  #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
  #define X86_FEATURE_FENCE_SWAPGS_KERNEL       (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
  #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
+ #define X86_FEATURE_PER_THREAD_MBA    (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
  
  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
  #define X86_FEATURE_AVX512_BF16               (12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@@ -353,7 -354,6 +354,7 @@@
  #define X86_FEATURE_CLDEMOTE          (16*32+25) /* CLDEMOTE instruction */
  #define X86_FEATURE_MOVDIRI           (16*32+27) /* MOVDIRI instruction */
  #define X86_FEATURE_MOVDIR64B         (16*32+28) /* MOVDIR64B instruction */
 +#define X86_FEATURE_ENQCMD            (16*32+29) /* ENQCMD and ENQCMDS instructions */
  
  /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
  #define X86_FEATURE_OVERFLOW_RECOV    (17*32+ 0) /* MCA overflow recovery support */
@@@ -369,7 -369,6 +370,7 @@@
  #define X86_FEATURE_MD_CLEAR          (18*32+10) /* VERW clears CPU buffers */
  #define X86_FEATURE_TSX_FORCE_ABORT   (18*32+13) /* "" TSX_FORCE_ABORT */
  #define X86_FEATURE_SERIALIZE         (18*32+14) /* SERIALIZE instruction */
 +#define X86_FEATURE_TSXLDTRK          (18*32+16) /* TSX Suspend Load Address Tracking */
  #define X86_FEATURE_PCONFIG           (18*32+18) /* Intel PCONFIG */
  #define X86_FEATURE_ARCH_LBR          (18*32+19) /* Intel ARCH LBR */
  #define X86_FEATURE_SPEC_CTRL         (18*32+26) /* "" Speculation Control (IBRS + IBPB) */

diff --combined arch/x86/kernel/cpu/cpuid-deps.c
index 3a02707c1f4d0b5be08f38e83e58a8d23b6d6b1b,3e30b26c50ef625b4a4f888ac8d6d1a9a03ffe92..d502241995a39df7f82ab16a723146d0eecb30d8
--- 1/arch/x86/kernel/cpu/cpuid-deps.c
--- 2/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@@ -69,7 -69,7 +69,8 @@@ static const struct cpuid_dep cpuid_dep
        { X86_FEATURE_CQM_MBM_TOTAL,            X86_FEATURE_CQM_LLC   },
        { X86_FEATURE_CQM_MBM_LOCAL,            X86_FEATURE_CQM_LLC   },
        { X86_FEATURE_AVX512_BF16,              X86_FEATURE_AVX512VL  },
 +      { X86_FEATURE_ENQCMD,                   X86_FEATURE_XSAVES    },
+       { X86_FEATURE_PER_THREAD_MBA,           X86_FEATURE_MBA       },
        {}
  };
  

diff --combined arch/x86/kernel/cpu/resctrl/core.c
index 9cceee61256976493f738df537b1451cc024f932,9e1712e8aef7ad2568018d28abf288533e2cb95f..e5f4ee8f4c3bbd7ed9b1c10e383fe28a190931ff
--- 1/arch/x86/kernel/cpu/resctrl/core.c
--- 2/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@@ -168,6 -168,7 +168,7 @@@ struct rdt_resource rdt_resources_all[
                .name                   = "MB",
                .domains                = domain_init(RDT_RESOURCE_MBA),
                .cache_level            = 3,
+               .parse_ctrlval          = parse_bw,
                .format_str             = "%d=%*u",
                .fflags                 = RFTYPE_RES_MB,
        },
@@@ -254,22 -255,30 +255,30 @@@ static bool __get_mem_config_intel(stru
  {
        union cpuid_0x10_3_eax eax;
        union cpuid_0x10_x_edx edx;
-       u32 ebx, ecx;
+       u32 ebx, ecx, max_delay;
  
        cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
        r->num_closid = edx.split.cos_max + 1;
-       r->membw.max_delay = eax.split.max_delay + 1;
+       max_delay = eax.split.max_delay + 1;
        r->default_ctrl = MAX_MBA_BW;
+       r->membw.arch_needs_linear = true;
        if (ecx & MBA_IS_LINEAR) {
                r->membw.delay_linear = true;
-               r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay;
-               r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay;
+               r->membw.min_bw = MAX_MBA_BW - max_delay;
+               r->membw.bw_gran = MAX_MBA_BW - max_delay;
        } else {
                if (!rdt_get_mb_table(r))
                        return false;
+               r->membw.arch_needs_linear = false;
        }
        r->data_width = 3;
  
+       if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA))
+               r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD;
+       else
+               r->membw.throttle_mode = THREAD_THROTTLE_MAX;
+       thread_throttle_mode_init();
+ 
        r->alloc_capable = true;
        r->alloc_enabled = true;
  
@@@ -288,7 -297,13 +297,13 @@@ static bool __rdt_get_mem_config_amd(st
  
        /* AMD does not use delay */
        r->membw.delay_linear = false;
+       r->membw.arch_needs_linear = false;
  
+       /*
+        * AMD does not use memory delay throttle model to control
+        * the allocation like Intel does.
+        */
+       r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED;
        r->membw.min_bw = 0;
        r->membw.bw_gran = 1;
        /* Max value is 2048, Data width should be 4 in decimal */
@@@ -346,19 -361,6 +361,6 @@@ static void rdt_get_cdp_l2_config(void
        rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);
  }
  
- static int get_cache_id(int cpu, int level)
- {
-       struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
-       int i;
- 
-       for (i = 0; i < ci->num_leaves; i++) {
-               if (ci->info_list[i].level == level)
-                       return ci->info_list[i].id;
-       }
- 
-       return -1;
- }
- 
  static void
  mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
  {
@@@ -556,13 -558,13 +558,13 @@@ static int domain_setup_mon_state(struc
   */
  static void domain_add_cpu(int cpu, struct rdt_resource *r)
  {
-       int id = get_cache_id(cpu, r->cache_level);
+       int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
        struct list_head *add_pos = NULL;
        struct rdt_domain *d;
  
        d = rdt_find_domain(r, id, &add_pos);
        if (IS_ERR(d)) {
 -              pr_warn("Could't find cache id for cpu %d\n", cpu);
 +              pr_warn("Couldn't find cache id for CPU %d\n", cpu);
                return;
        }
  
@@@ -602,12 -604,12 +604,12 @@@
  
  static void domain_remove_cpu(int cpu, struct rdt_resource *r)
  {
-       int id = get_cache_id(cpu, r->cache_level);
+       int id = get_cpu_cacheinfo_id(cpu, r->cache_level);
        struct rdt_domain *d;
  
        d = rdt_find_domain(r, id, NULL);
        if (IS_ERR_OR_NULL(d)) {
 -              pr_warn("Could't find cache id for cpu %d\n", cpu);
 +              pr_warn("Couldn't find cache id for CPU %d\n", cpu);
                return;
        }
  
@@@ -918,12 -920,12 +920,12 @@@ static __init void rdt_init_res_defs_in
                    r->rid == RDT_RESOURCE_L3CODE ||
                    r->rid == RDT_RESOURCE_L2 ||
                    r->rid == RDT_RESOURCE_L2DATA ||
-                   r->rid == RDT_RESOURCE_L2CODE)
-                       r->cbm_validate = cbm_validate_intel;
-               else if (r->rid == RDT_RESOURCE_MBA) {
+                   r->rid == RDT_RESOURCE_L2CODE) {
+                       r->cache.arch_has_sparse_bitmaps = false;
+                       r->cache.arch_has_empty_bitmaps = false;
+               } else if (r->rid == RDT_RESOURCE_MBA) {
                        r->msr_base = MSR_IA32_MBA_THRTL_BASE;
                        r->msr_update = mba_wrmsr_intel;
-                       r->parse_ctrlval = parse_bw_intel;
                }
        }
  }
@@@ -938,12 -940,12 +940,12 @@@ static __init void rdt_init_res_defs_am
                    r->rid == RDT_RESOURCE_L3CODE ||
                    r->rid == RDT_RESOURCE_L2 ||
                    r->rid == RDT_RESOURCE_L2DATA ||
-                   r->rid == RDT_RESOURCE_L2CODE)
-                       r->cbm_validate = cbm_validate_amd;
-               else if (r->rid == RDT_RESOURCE_MBA) {
+                   r->rid == RDT_RESOURCE_L2CODE) {
+                       r->cache.arch_has_sparse_bitmaps = true;
+                       r->cache.arch_has_empty_bitmaps = true;
+               } else if (r->rid == RDT_RESOURCE_MBA) {
                        r->msr_base = MSR_IA32_MBA_BW_BASE;
                        r->msr_update = mba_wrmsr_amd;
-                       r->parse_ctrlval = parse_bw_amd;
                }
        }
  }

diff --combined arch/x86/kernel/cpu/scattered.c
index 3221b71a0df8364b5eecf6aba72523a74cb28516,bccfc9ff3cc12be6ae1c965e99ac9019dd877620..2eb0a8c44b352216b62691b0be15c4a068257179
--- 1/arch/x86/kernel/cpu/scattered.c
--- 2/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@@ -35,13 -35,13 +35,14 @@@ static const struct cpuid_bit cpuid_bit
        { X86_FEATURE_CDP_L3,           CPUID_ECX,  2, 0x00000010, 1 },
        { X86_FEATURE_CDP_L2,           CPUID_ECX,  2, 0x00000010, 2 },
        { X86_FEATURE_MBA,              CPUID_EBX,  3, 0x00000010, 0 },
+       { X86_FEATURE_PER_THREAD_MBA,   CPUID_ECX,  0, 0x00000010, 3 },
        { X86_FEATURE_HW_PSTATE,        CPUID_EDX,  7, 0x80000007, 0 },
        { X86_FEATURE_CPB,              CPUID_EDX,  9, 0x80000007, 0 },
        { X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
        { X86_FEATURE_MBA,              CPUID_EBX,  6, 0x80000008, 0 },
        { X86_FEATURE_SME,              CPUID_EAX,  0, 0x8000001f, 0 },
        { X86_FEATURE_SEV,              CPUID_EAX,  1, 0x8000001f, 0 },
 +      { X86_FEATURE_SME_COHERENT,     CPUID_EAX, 10, 0x8000001f, 0 },
        { 0, 0, 0, 0, 0 }
  };