clk: mediatek: Change PLL register API for MT8186

Use mtk_clk_register_pllfhs() to enhance frequency hopping and
spread spectrum clocking control for MT8186.

Co-developed-by: Edward-JW Yang <[email protected]>
Signed-off-by: Edward-JW Yang <[email protected]>
Signed-off-by: Johnson Wang <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Chen-Yu Tsai <[email protected]>

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 38f667eadda3917cd7157312b410eea6da40d25f..22e8e79475ee4fd6724b8cca826df59bfa61d44e 100644 (file)
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -560,6 +560,7 @@ config COMMON_CLK_MT8186
        bool "Clock driver for MediaTek MT8186"
        depends on ARM64 || COMPILE_TEST
        select COMMON_CLK_MEDIATEK
+       select COMMON_CLK_MEDIATEK_FHCTL
        default ARCH_MEDIATEK
        help
          This driver supports MediaTek MT8186 clocks.

diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
index e692a2a67ce1cd6470e2d89a39701fc3aa98dac9..1d673c6278a9dc354ae850eed32e2c44cf91fe5c 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c
@@ -9,6 +9,7 @@
 
 #include "clk-mtk.h"
 #include "clk-pll.h"
+#include "clk-pllfh.h"
 
 #define MT8186_PLL_FMAX                (3800UL * MHZ)
 #define MT8186_PLL_FMIN                (1500UL * MHZ)
@@ -76,6 +77,59 @@ static const struct mtk_pll_data plls[] = {
            0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
 };
 
+enum fh_pll_id {
+       FH_ARMPLL_LL,
+       FH_ARMPLL_BL,
+       FH_CCIPLL,
+       FH_MAINPLL,
+       FH_MMPLL,
+       FH_TVDPLL,
+       FH_RESERVE6,
+       FH_ADSPPLL,
+       FH_MFGPLL,
+       FH_NNAPLL,
+       FH_NNA2PLL,
+       FH_MSDCPLL,
+       FH_RESERVE12,
+       FH_NR_FH,
+};
+
+#define FH(_pllid, _fhid, _offset) {                                   \
+               .data = {                                               \
+                       .pll_id = _pllid,                               \
+                       .fh_id = _fhid,                                 \
+                       .fhx_offset = _offset,                          \
+                       .dds_mask = GENMASK(21, 0),                     \
+                       .slope0_value = 0x6003c97,                      \
+                       .slope1_value = 0x6003c97,                      \
+                       .sfstrx_en = BIT(2),                            \
+                       .frddsx_en = BIT(1),                            \
+                       .fhctlx_en = BIT(0),                            \
+                       .tgl_org = BIT(31),                             \
+                       .dvfs_tri = BIT(31),                            \
+                       .pcwchg = BIT(31),                              \
+                       .dt_val = 0x0,                                  \
+                       .df_val = 0x9,                                  \
+                       .updnlmt_shft = 16,                             \
+                       .msk_frddsx_dys = GENMASK(23, 20),              \
+                       .msk_frddsx_dts = GENMASK(19, 16),              \
+               },                                                      \
+       }
+
+static struct mtk_pllfh_data pllfhs[] = {
+       FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C),
+       FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050),
+       FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064),
+       FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
+       FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
+       FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
+       FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8),
+       FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC),
+       FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0),
+       FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104),
+       FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
+};
+
 static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
        { .compatible = "mediatek,mt8186-apmixedsys", },
        {}
@@ -85,13 +139,17 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
 {
        struct clk_hw_onecell_data *clk_data;
        struct device_node *node = pdev->dev.of_node;
+       const u8 *fhctl_node = "mediatek,mt8186-fhctl";
        int r;
 
        clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
        if (!clk_data)
                return -ENOMEM;
 
-       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+       fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+
+       r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+                                   pllfhs, ARRAY_SIZE(pllfhs), clk_data);
        if (r)
                goto free_apmixed_data;
 
@@ -104,7 +162,8 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
        return r;
 
 unregister_plls:
-       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+       mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+                                 ARRAY_SIZE(pllfhs), clk_data);
 free_apmixed_data:
        mtk_free_clk_data(clk_data);
        return r;
@@ -116,7 +175,8 @@ static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
        struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
 
        of_clk_del_provider(node);
-       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+       mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+                                 ARRAY_SIZE(pllfhs), clk_data);
        mtk_free_clk_data(clk_data);
 
        return 0;