This enables support for the Broadcom BCM2835 SoC. This SoC is
use in the Raspberry Pi, and Roku 2 devices.
-config ARCH_BCMRING
- bool "Broadcom BCMRING"
- depends on MMU
- select CPU_V6
- select ARM_AMBA
- select ARM_TIMER_SP804
- select CLKDEV_LOOKUP
- select GENERIC_CLOCKEVENTS
- select ARCH_WANT_OPTIONAL_GPIOLIB
- help
- Support for Broadcom's BCMRing platform.
-
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
+ select COMMON_CLK
+ select CLKDEV_LOOKUP
select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x/731x based boards.
select CLKSRC_MMIO
select COMMON_CLK
select HAVE_CLK_PREPARE
+ select MULTI_IRQ_HANDLER
select PINCTRL
+ select SPARSE_IRQ
select USE_OF
help
Support for Freescale MXS-based family of processors
config ARCH_DOVE
bool "Marvell Dove"
select CPU_V7
- select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select PLAT_ORION
+ select MIGHT_HAVE_PCI
+ select PLAT_ORION_LEGACY
+ select USB_ARCH_HAS_EHCI
help
Support for the Marvell Dove SoC 88AP510
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select PLAT_ORION
+ select PLAT_ORION_LEGACY
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select PLAT_ORION
+ select PLAT_ORION_LEGACY
help
Support for the following Marvell MV78xx0 series SoCs:
MV781x0, MV782x0.
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select PLAT_ORION
+ select PLAT_ORION_LEGACY
help
Support for the following Marvell Orion 5x series SoCs:
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select PINCTRL
+ select PINCTRL_STN8815
select MIGHT_HAVE_CACHE_L2X0
select ARCH_REQUIRE_GPIOLIB
help
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
+ select USE_OF
+ select COMMON_CLK
+ select HAVE_CLK
+ select CLKDEV_LOOKUP
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
source "arch/arm/mach-at91/Kconfig"
-source "arch/arm/mach-bcmring/Kconfig"
-
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
-source "arch/arm/mach-vt8500/Kconfig"
-
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
select IRQ_DOMAIN
select COMMON_CLK
+ config PLAT_ORION_LEGACY
+ bool
+ select PLAT_ORION
+
config PLAT_PXA
bool
default 355 if ARCH_U8500
default 264 if MACH_H4700
default 512 if SOC_OMAP5
+ default 288 if ARCH_VT8500
default 0
help
Maximum number of GPIOs in the system.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
-config LEDS
- bool "Timer and CPU usage LEDs"
- depends on ARCH_CDB89712 || ARCH_EBSA110 || \
- ARCH_EBSA285 || ARCH_INTEGRATOR || \
- ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
- ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
- ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
- ARCH_AT91 || ARCH_DAVINCI || \
- ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
- help
- If you say Y here, the LEDs on your machine will be used
- to provide useful information about your current system status.
-
- If you are compiling a kernel for a NetWinder or EBSA-285, you will
- be able to select which LEDs are active using the options below. If
- you are compiling a kernel for the EBSA-110 or the LART however, the
- red LED will simply flash regularly to indicate that the system is
- still functional. It is safe to say Y here if you have a CATS
- system, but the driver will do nothing.
-
-config LEDS_TIMER
- bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
- OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
- || MACH_OMAP_PERSEUS2
- depends on LEDS
- depends on !GENERIC_CLOCKEVENTS
- default y if ARCH_EBSA110
- help
- If you say Y here, one of the system LEDs (the green one on the
- NetWinder, the amber one on the EBSA285, or the red one on the LART)
- will flash regularly to indicate that the system is still
- operational. This is mainly useful to kernel hackers who are
- debugging unstable kernels.
-
- The LART uses the same LED for both Timer LED and CPU usage LED
- functions. You may choose to use both, but the Timer LED function
- will overrule the CPU usage LED.
-
-config LEDS_CPU
- bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
- !ARCH_OMAP) \
- || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
- || MACH_OMAP_PERSEUS2
- depends on LEDS
- help
- If you say Y here, the red LED will be used to give a good real
- time indication of CPU usage, by lighting whenever the idle task
- is not currently executing.
-
- The LART uses the same LED for both Timer LED and CPU usage LED
- functions. You may choose to use both, but the Timer LED function
- will overrule the CPU usage LED.
-
config ALIGNMENT_TRAP
bool
depends on CPU_CP15_MMU
This was deprecated in 2001 and announced to live on for 5 years.
Some old boot loaders still use this way.
+config XEN_DOM0
+ def_bool y
+ depends on XEN
+
+config XEN
+ bool "Xen guest support on ARM (EXPERIMENTAL)"
+ depends on EXPERIMENTAL && ARM && OF
+ help
+ Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
+
endmenu
menu "Boot options"
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
- depends on !ARCH_S5PC100 && !ARCH_TEGRA
+ depends on !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
def_bool y
usb_a9263.dtb \
usb_a9g20.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+ dove-cubox.dtb \
+ dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
+ exynos4210-trats.dtb \
exynos5250-smdk5250.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-dns325.dtb \
+ kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
kirkwood-goflexnet.dtb \
kirkwood-ib62x0.dtb \
kirkwood-iconnect.dtb \
+ kirkwood-iomega_ix2_200.dtb \
+ kirkwood-km_kirkwood.dtb \
kirkwood-lschlv2.dtb \
kirkwood-lsxhl.dtb \
kirkwood-ts219-6281.dtb \
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb \
- vexpress-v2p-ca15_a7.dtb
+ vexpress-v2p-ca15_a7.dtb \
+ xenvm-4.2.dtb
endif
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
+ obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
-# L3 interconnect
-obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
-obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o
-
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
return;
}
clk_set_rate(phy_ref_clk, 19200000);
- clk_enable(phy_ref_clk);
+ clk_prepare_enable(phy_ref_clk);
/* disable the power to the usb hub prior to init and reset phy+hub */
ret = gpio_request_array(panda_ehci_gpios,
.audpwron_gpio = 127,
};
+static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("twl6040", 0x4b),
+ .irq = 119 + OMAP44XX_IRQ_GIC_START,
+ .platform_data = &twl6040_data,
+ },
+};
+
/* Panda board uses the common PMIC configuration */
static struct twl4030_platform_data omap4_panda_twldata;
TWL_COMMON_REGULATOR_CLK32KG |
TWL_COMMON_REGULATOR_V1V8 |
TWL_COMMON_REGULATOR_V2V1);
- omap4_pmic_init("twl6030", &omap4_panda_twldata,
- &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START);
+ omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
+ ARRAY_SIZE(panda_i2c_1_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
/*
* Bus 3 is attached to the DVI port where devices like the pico DLP
const int id;
};
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
{ "dss_core", "omapdss_dss", -1 },
{ "dss_dispc", "omapdss_dispc", -1 },
{ "dss_rfbi", "omapdss_rfbi", -1 },
{ "dss_venc", "omapdss_venc", -1 },
};
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
{ "dss_core", "omapdss_dss", -1 },
{ "dss_dispc", "omapdss_dispc", -1 },
{ "dss_rfbi", "omapdss_rfbi", -1 },
{ "dss_dsi1", "omapdss_dsi", 0 },
};
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
{ "dss_core", "omapdss_dss", -1 },
{ "dss_dispc", "omapdss_dispc", -1 },
{ "dss_rfbi", "omapdss_rfbi", -1 },
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
- clk_enable(oc->_clk);
+ clk_prepare_enable(oc->_clk);
dispc_disable_outputs();
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
if (oc->_clk)
- clk_disable(oc->_clk);
+ clk_disable_unprepare(oc->_clk);
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
#include <plat/mmc.h>
#include <plat/dmtimer.h>
#include <plat/common.h>
+ #include <plat/iommu.h>
#include "omap_hwmod_common_data.h"
#include "cm1_44xx.h"
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+ .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
};
.name = "mpu_private",
.class = &omap44xx_mpu_bus_hwmod_class,
.clkdm_name = "mpuss_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/*
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+ .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
.mpu_irqs = omap44xx_ctrl_module_core_irqs,
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* ctrl_module_pad_core */
.name = "ctrl_module_pad_core",
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* ctrl_module_wkup */
.name = "ctrl_module_wkup",
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* ctrl_module_pad_wkup */
.name = "ctrl_module_pad_wkup",
.class = &omap44xx_ctrl_module_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/*
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
{ .name = "dsp", .rst_shift = 0 },
- { .name = "mmu_cache", .rst_shift = 1 },
};
static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "gpmc",
.class = &omap44xx_gpmc_hwmod_class,
.clkdm_name = "l3_2_clkdm",
+ /*
+ * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+ * block. It is not being added due to any known bugs with
+ * resetting the GPMC IP block, but rather because any timings
+ * set by the bootloader are not being correctly programmed by
+ * the kernel from the board file or DT data.
+ * HWMOD_INIT_NO_RESET should be removed ASAP.
+ */
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_gpmc_irqs,
.sdma_reqs = omap44xx_gpmc_sdma_reqs,
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
{ .name = "cpu0", .rst_shift = 0 },
{ .name = "cpu1", .rst_shift = 1 },
- { .name = "mmu_cache", .rst_shift = 2 },
};
static struct omap_hwmod omap44xx_ipu_hwmod = {
},
};
+ /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+ static struct omap_hwmod_class_sysconfig mmu_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+ static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+ .name = "mmu",
+ .sysc = &mmu_sysc,
+ };
+
+ /* mmu ipu */
+
+ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
+ .da_start = 0x0,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 32,
+ };
+
+ static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
+ { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
+ { .name = "mmu_cache", .rst_shift = 2 },
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
+ {
+ .pa_start = 0x55082000,
+ .pa_end = 0x550820ff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+ };
+
+ /* l3_main_2 -> mmu_ipu */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
+ .master = &omap44xx_l3_main_2_hwmod,
+ .slave = &omap44xx_mmu_ipu_hwmod,
+ .clk = "l3_div_ck",
+ .addr = omap44xx_mmu_ipu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
+ .name = "mmu_ipu",
+ .class = &omap44xx_mmu_hwmod_class,
+ .clkdm_name = "ducati_clkdm",
+ .mpu_irqs = omap44xx_mmu_ipu_irqs,
+ .rst_lines = omap44xx_mmu_ipu_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
+ .main_clk = "ducati_clk_mux_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .dev_attr = &mmu_ipu_dev_attr,
+ };
+
+ /* mmu dsp */
+
+ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
+ .da_start = 0x0,
+ .da_end = 0xfffff000,
+ .nr_tlb_entries = 32,
+ };
+
+ static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
+ static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
+ { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+ };
+
+ static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
+ { .name = "mmu_cache", .rst_shift = 1 },
+ };
+
+ static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
+ {
+ .pa_start = 0x4a066000,
+ .pa_end = 0x4a0660ff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+ };
+
+ /* l4_cfg -> dsp */
+ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
+ .master = &omap44xx_l4_cfg_hwmod,
+ .slave = &omap44xx_mmu_dsp_hwmod,
+ .clk = "l4_div_ck",
+ .addr = omap44xx_mmu_dsp_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
+ .name = "mmu_dsp",
+ .class = &omap44xx_mmu_hwmod_class,
+ .clkdm_name = "tesla_clkdm",
+ .mpu_irqs = omap44xx_mmu_dsp_irqs,
+ .rst_lines = omap44xx_mmu_dsp_resets,
+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
+ .main_clk = "dpll_iva_m4x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .dev_attr = &mmu_dsp_dev_attr,
+ };
+
/*
* 'mpu' class
* mpu sub-system
/* mpu */
static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+ { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+ { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
* protocol
*/
+ static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
.name = "ocp2scp",
+ .sysc = &omap44xx_ocp2scp_sysc,
};
/* ocp2scp_usb_phy */
- static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
- { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
- };
-
static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
.name = "ocp2scp_usb_phy",
.class = &omap44xx_ocp2scp_hwmod_class,
.clkdm_name = "l3_init_clkdm",
+ .main_clk = "ocp2scp_usb_phy_phy_48m",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_HWCTRL,
},
},
- .opt_clks = ocp2scp_usb_phy_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
};
/*
.name = "prcm_mpu",
.class = &omap44xx_prcm_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
+ .flags = HWMOD_NO_IDLEST,
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* cm_core_aon */
static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
.name = "cm_core_aon",
.class = &omap44xx_prcm_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* cm_core */
static struct omap_hwmod omap44xx_cm_core_hwmod = {
.name = "cm_core",
.class = &omap44xx_prcm_hwmod_class,
+ .flags = HWMOD_NO_IDLEST,
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/* prm */
.name = "scrm",
.class = &omap44xx_scrm_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
};
/*
.timer_capability = OMAP_TIMER_HAS_PWM,
};
+ /* timers with DSP interrupt dev attribute */
+ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
+ };
+
+ /* pwm timers with DSP interrupt dev attribute */
+ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+ };
+
/* timer1 */
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer6 */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer7 */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .dev_attr = &capability_dsp_dev_attr,
};
/* timer8 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
+ .dev_attr = &capability_dsp_pwm_dev_attr,
};
/* timer9 */
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+ static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
+ {
+ .pa_start = 0x4a0ad000,
+ .pa_end = 0x4a0ad01f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+ };
+
/* l4_cfg -> ocp2scp_usb_phy */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_ocp2scp_usb_phy_hwmod,
.clk = "l4_div_ck",
+ .addr = omap44xx_ocp2scp_usb_phy_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
{
.pa_start = 0x4a0ab000,
- .pa_end = 0x4a0ab003,
+ .pa_end = 0x4a0ab7ff,
.flags = ADDR_TYPE_RT
},
+ {
+ /* XXX: Remove this once control module driver is in place */
+ .pa_start = 0x4a00233c,
+ .pa_end = 0x4a00233f,
+ .flags = ADDR_TYPE_RT
+ },
{ }
};
&omap44xx_l4_per__mmc3,
&omap44xx_l4_per__mmc4,
&omap44xx_l4_per__mmc5,
+ &omap44xx_l3_main_2__mmu_ipu,
+ &omap44xx_l4_cfg__mmu_dsp,
&omap44xx_l3_main_2__ocmc_ram,
&omap44xx_l4_cfg__ocp2scp_usb_phy,
&omap44xx_mpu_private__prcm_mpu,
****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
{
- .virtual = ORION5X_REGS_VIRT_BASE,
+ .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
.length = ORION5X_REGS_SIZE,
.type = MT_DEVICE,
}, {
- .virtual = ORION5X_PCIE_WA_VIRT_BASE,
+ .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
.length = ORION5X_PCIE_WA_SIZE,
.type = MT_DEVICE,
void __init orion5x_init_early(void)
{
orion_time_set_base(TIMER_VIRT_BASE);
+
+ /*
+ * Some Orion5x devices allocate their coherent buffers from atomic
+ * context. Increase size of atomic coherent pool to make sure such
+ * the allocations won't fail.
+ */
+ init_dma_coherent_pool_size(SZ_1M);
}
int orion5x_tclk;
config GPIO_DA9052
tristate "Dialog DA9052 GPIO"
- depends on PMIC_DA9052 && BROKEN
+ depends on PMIC_DA9052
help
Say yes here to enable the GPIO driver for the DA9052 chip.
Qualcomm MSM chips. Most of the pins on the MSM can be
selected for GPIO, and are controlled by this driver.
+ config GPIO_MVEBU
+ def_bool y
+ depends on ARCH_MVEBU
+ select GPIO_GENERIC
+ select GENERIC_IRQ_CHIP
+
config GPIO_MXC
def_bool y
depends on ARCH_MXC
Say yes here to support the STA2x11/ConneXt GPIO device.
The GPIO module has 128 GPIO pins with alternate functions.
+config GPIO_VT8500
+ bool "VIA/Wondermedia SoC GPIO Support"
+ depends on ARCH_VT8500
+ help
+ Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
config GPIO_XILINX
bool "Xilinx GPIO support"
depends on PPC_OF || MICROBLAZE
config GPIO_PCF857X
tristate "PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders"
depends on I2C
+ select IRQ_DOMAIN
help
Say yes here to provide access to most "quasi-bidirectional" I2C
GPIO expanders used for additional digital outputs or inputs.
Say yes here to access the GPIO signals of various multi-function
power management chips from Texas Instruments.
+config GPIO_TWL6040
+ tristate "TWL6040 GPO"
+ depends on TWL6040_CORE
+ help
+ Say yes here to access the GPO signals of twl6040
+ audio chip from Texas Instruments.
+
config GPIO_WM831X
tristate "WM831x GPIOs"
depends on MFD_WM831X
Say yes here to enable the adp5588 to be used as an interrupt
controller. It requires the driver to be built in the kernel.
+config GPIO_ADNP
+ tristate "Avionic Design N-bit GPIO expander"
+ depends on I2C && OF
+ help
+ This option enables support for N GPIOs found on Avionic Design
+ I2C GPIO expanders. The register space will be extended by powers
+ of two, so the controller will need to accomodate for that. For
+ example: if a controller provides 48 pins, 6 registers will be
+ enough to represent all pins, but the driver will assume a
+ register layout for 64 pins (8 registers).
+
comment "PCI GPIO expanders:"
config GPIO_CS5535
obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
obj-$(CONFIG_GPIO_AB8500) += gpio-ab8500.o
+obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o
obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
+ obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o
+obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o
obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o
obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500) += gpio-vt8500.o
obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
help
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
+config PINCTRL_BCM2835
+ bool
+ select PINMUX
+ select PINCONF
+
config PINCTRL_IMX
bool
select PINMUX
select PINCONF
+config PINCTRL_IMX35
+ bool "IMX35 pinctrl driver"
+ depends on OF
+ depends on SOC_IMX35
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx35 pinctrl driver
+
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
depends on OF
select PINMUX
select PINCONF
+config PINCTRL_STN8815
+ bool "STN8815 pin controller driver"
+ depends on PINCTRL_NOMADIK && ARCH_NOMADIK
+
config PINCTRL_DB8500
bool "DB8500 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
+config PINCTRL_DB8540
+ bool "DB8540 pin controller driver"
+ depends on PINCTRL_NOMADIK && ARCH_U8500
+
config PINCTRL_PXA168
bool "PXA168 pin controller driver"
depends on ARCH_MMP
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_SAMSUNG
+ bool "Samsung pinctrl driver"
+ select PINMUX
+ select PINCONF
+
+config PINCTRL_EXYNOS4
+ bool "Pinctrl driver data for Exynos4 SoC"
+ select PINCTRL_SAMSUNG
+
+ config PINCTRL_MVEBU
+ bool
+ depends on ARCH_MVEBU
+ select PINMUX
+ select PINCONF
+
+ config PINCTRL_DOVE
+ bool
+ select PINCTRL_MVEBU
+
+ config PINCTRL_KIRKWOOD
+ bool
+ select PINCTRL_MVEBU
+
+ config PINCTRL_ARMADA_370
+ bool
+ select PINCTRL_MVEBU
+
+ config PINCTRL_ARMADA_XP
+ bool
+ select PINCTRL_MVEBU
+
source "drivers/pinctrl/spear/Kconfig"
endmenu
obj-$(CONFIG_PINCTRL) += devicetree.o
endif
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
+obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
+obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
+obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
+obj-$(CONFIG_PINCTRL_EXYNOS4) += pinctrl-exynos.o
+ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
+ obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
+ obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
+ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+ obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
obj-$(CONFIG_PLAT_SPEAR) += spear/
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/err.h>
#include <linux/spi/spi.h>
- #include <plat/clock.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#define OMAP2_MCSPI_MAX_FREQ 48000000
u32 chconf0;
};
-#define MOD_REG_BIT(val, mask, set) do { \
- if (set) \
- val |= mask; \
- else \
- val &= ~mask; \
-} while (0)
-
static inline void mcspi_write_reg(struct spi_master *master,
int idx, u32 val)
{
else
rw = OMAP2_MCSPI_CHCONF_DMAW;
- MOD_REG_BIT(l, rw, enable);
+ if (enable)
+ l |= rw;
+ else
+ l &= ~rw;
+
mcspi_write_chconf0(spi, l);
}
u32 l;
l = mcspi_cached_chconf0(spi);
- MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
+ if (cs_active)
+ l |= OMAP2_MCSPI_CHCONF_FORCE;
+ else
+ l &= ~OMAP2_MCSPI_CHCONF_FORCE;
+
mcspi_write_chconf0(spi, l);
}
* to single-channel master mode
*/
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
- MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
- MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
- MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
+ l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
+ l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
ctx->modulctrl = l;
list_for_each_entry(cs, &ctx->cs, node)
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
}
-static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
-{
- pm_runtime_mark_last_busy(mcspi->dev);
- pm_runtime_put_autosuspend(mcspi->dev);
-}
-
-static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
-{
- return pm_runtime_get_sync(mcspi->dev);
-}
static int omap2_prepare_transfer(struct spi_master *master)
{
omap2_mcspi_set_dma_req(spi, 0, 0);
}
-static unsigned
-omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
+static void omap2_mcspi_tx_dma(struct spi_device *spi,
+ struct spi_transfer *xfer,
+ struct dma_slave_config cfg)
{
struct omap2_mcspi *mcspi;
- struct omap2_mcspi_cs *cs = spi->controller_state;
struct omap2_mcspi_dma *mcspi_dma;
unsigned int count;
- int word_len, element_count;
- int elements = 0;
- u32 l;
u8 * rx;
const u8 * tx;
void __iomem *chstat_reg;
- struct dma_slave_config cfg;
- enum dma_slave_buswidth width;
- unsigned es;
+ struct omap2_mcspi_cs *cs = spi->controller_state;
mcspi = spi_master_get_devdata(spi->master);
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
- l = mcspi_cached_chconf0(spi);
+ count = xfer->len;
+ rx = xfer->rx_buf;
+ tx = xfer->tx_buf;
chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
- if (cs->word_len <= 8) {
- width = DMA_SLAVE_BUSWIDTH_1_BYTE;
- es = 1;
- } else if (cs->word_len <= 16) {
- width = DMA_SLAVE_BUSWIDTH_2_BYTES;
- es = 2;
- } else {
- width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- es = 4;
- }
-
- memset(&cfg, 0, sizeof(cfg));
- cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
- cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
- cfg.src_addr_width = width;
- cfg.dst_addr_width = width;
- cfg.src_maxburst = 1;
- cfg.dst_maxburst = 1;
-
- if (xfer->tx_buf && mcspi_dma->dma_tx) {
+ if (mcspi_dma->dma_tx) {
struct dma_async_tx_descriptor *tx;
struct scatterlist sg;
sg_dma_len(&sg) = xfer->len;
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
- DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (tx) {
tx->callback = omap2_mcspi_tx_callback;
tx->callback_param = spi;
/* FIXME: fall back to PIO? */
}
}
+ dma_async_issue_pending(mcspi_dma->dma_tx);
+ omap2_mcspi_set_dma_req(spi, 0, 1);
+
+ wait_for_completion(&mcspi_dma->dma_tx_completion);
+ dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
+ DMA_TO_DEVICE);
+
+ /* for TX_ONLY mode, be sure all words have shifted out */
+ if (rx == NULL) {
+ if (mcspi_wait_for_reg_bit(chstat_reg,
+ OMAP2_MCSPI_CHSTAT_TXS) < 0)
+ dev_err(&spi->dev, "TXS timed out\n");
+ else if (mcspi_wait_for_reg_bit(chstat_reg,
+ OMAP2_MCSPI_CHSTAT_EOT) < 0)
+ dev_err(&spi->dev, "EOT timed out\n");
+ }
+}
+
+static unsigned
+omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
+ struct dma_slave_config cfg,
+ unsigned es)
+{
+ struct omap2_mcspi *mcspi;
+ struct omap2_mcspi_dma *mcspi_dma;
+ unsigned int count;
+ u32 l;
+ int elements = 0;
+ int word_len, element_count;
+ struct omap2_mcspi_cs *cs = spi->controller_state;
+ mcspi = spi_master_get_devdata(spi->master);
+ mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ count = xfer->len;
+ word_len = cs->word_len;
+ l = mcspi_cached_chconf0(spi);
- if (xfer->rx_buf && mcspi_dma->dma_rx) {
+ if (word_len <= 8)
+ element_count = count;
+ else if (word_len <= 16)
+ element_count = count >> 1;
+ else /* word_len <= 32 */
+ element_count = count >> 2;
+
+ if (mcspi_dma->dma_rx) {
struct dma_async_tx_descriptor *tx;
struct scatterlist sg;
size_t len = xfer->len - es;
sg_dma_len(&sg) = len;
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
- DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
+ DMA_CTRL_ACK);
if (tx) {
tx->callback = omap2_mcspi_rx_callback;
tx->callback_param = spi;
dmaengine_submit(tx);
} else {
- /* FIXME: fall back to PIO? */
- }
- }
-
- count = xfer->len;
- word_len = cs->word_len;
-
- rx = xfer->rx_buf;
- tx = xfer->tx_buf;
-
- if (word_len <= 8) {
- element_count = count;
- } else if (word_len <= 16) {
- element_count = count >> 1;
- } else /* word_len <= 32 */ {
- element_count = count >> 2;
- }
-
- if (tx != NULL) {
- dma_async_issue_pending(mcspi_dma->dma_tx);
- omap2_mcspi_set_dma_req(spi, 0, 1);
- }
-
- if (rx != NULL) {
- dma_async_issue_pending(mcspi_dma->dma_rx);
- omap2_mcspi_set_dma_req(spi, 1, 1);
- }
-
- if (tx != NULL) {
- wait_for_completion(&mcspi_dma->dma_tx_completion);
- dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
- DMA_TO_DEVICE);
-
- /* for TX_ONLY mode, be sure all words have shifted out */
- if (rx == NULL) {
- if (mcspi_wait_for_reg_bit(chstat_reg,
- OMAP2_MCSPI_CHSTAT_TXS) < 0)
- dev_err(&spi->dev, "TXS timed out\n");
- else if (mcspi_wait_for_reg_bit(chstat_reg,
- OMAP2_MCSPI_CHSTAT_EOT) < 0)
- dev_err(&spi->dev, "EOT timed out\n");
+ /* FIXME: fall back to PIO? */
}
}
- if (rx != NULL) {
- wait_for_completion(&mcspi_dma->dma_rx_completion);
- dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
- DMA_FROM_DEVICE);
- omap2_mcspi_set_enable(spi, 0);
+ dma_async_issue_pending(mcspi_dma->dma_rx);
+ omap2_mcspi_set_dma_req(spi, 1, 1);
- elements = element_count - 1;
+ wait_for_completion(&mcspi_dma->dma_rx_completion);
+ dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
+ DMA_FROM_DEVICE);
+ omap2_mcspi_set_enable(spi, 0);
- if (l & OMAP2_MCSPI_CHCONF_TURBO) {
- elements--;
+ elements = element_count - 1;
- if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
- & OMAP2_MCSPI_CHSTAT_RXS)) {
- u32 w;
-
- w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
- if (word_len <= 8)
- ((u8 *)xfer->rx_buf)[elements++] = w;
- else if (word_len <= 16)
- ((u16 *)xfer->rx_buf)[elements++] = w;
- else /* word_len <= 32 */
- ((u32 *)xfer->rx_buf)[elements++] = w;
- } else {
- dev_err(&spi->dev,
- "DMA RX penultimate word empty");
- count -= (word_len <= 8) ? 2 :
- (word_len <= 16) ? 4 :
- /* word_len <= 32 */ 8;
- omap2_mcspi_set_enable(spi, 1);
- return count;
- }
- }
+ if (l & OMAP2_MCSPI_CHCONF_TURBO) {
+ elements--;
if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
- & OMAP2_MCSPI_CHSTAT_RXS)) {
+ & OMAP2_MCSPI_CHSTAT_RXS)) {
u32 w;
w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
if (word_len <= 8)
- ((u8 *)xfer->rx_buf)[elements] = w;
+ ((u8 *)xfer->rx_buf)[elements++] = w;
else if (word_len <= 16)
- ((u16 *)xfer->rx_buf)[elements] = w;
+ ((u16 *)xfer->rx_buf)[elements++] = w;
else /* word_len <= 32 */
- ((u32 *)xfer->rx_buf)[elements] = w;
+ ((u32 *)xfer->rx_buf)[elements++] = w;
} else {
- dev_err(&spi->dev, "DMA RX last word empty");
- count -= (word_len <= 8) ? 1 :
- (word_len <= 16) ? 2 :
- /* word_len <= 32 */ 4;
+ dev_err(&spi->dev, "DMA RX penultimate word empty");
+ count -= (word_len <= 8) ? 2 :
+ (word_len <= 16) ? 4 :
+ /* word_len <= 32 */ 8;
+ omap2_mcspi_set_enable(spi, 1);
+ return count;
}
- omap2_mcspi_set_enable(spi, 1);
}
+ if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
+ & OMAP2_MCSPI_CHSTAT_RXS)) {
+ u32 w;
+
+ w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
+ if (word_len <= 8)
+ ((u8 *)xfer->rx_buf)[elements] = w;
+ else if (word_len <= 16)
+ ((u16 *)xfer->rx_buf)[elements] = w;
+ else /* word_len <= 32 */
+ ((u32 *)xfer->rx_buf)[elements] = w;
+ } else {
+ dev_err(&spi->dev, "DMA RX last word empty");
+ count -= (word_len <= 8) ? 1 :
+ (word_len <= 16) ? 2 :
+ /* word_len <= 32 */ 4;
+ }
+ omap2_mcspi_set_enable(spi, 1);
+ return count;
+}
+
+static unsigned
+omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
+{
+ struct omap2_mcspi *mcspi;
+ struct omap2_mcspi_cs *cs = spi->controller_state;
+ struct omap2_mcspi_dma *mcspi_dma;
+ unsigned int count;
+ u32 l;
+ u8 *rx;
+ const u8 *tx;
+ struct dma_slave_config cfg;
+ enum dma_slave_buswidth width;
+ unsigned es;
+
+ mcspi = spi_master_get_devdata(spi->master);
+ mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+ l = mcspi_cached_chconf0(spi);
+
+
+ if (cs->word_len <= 8) {
+ width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+ es = 1;
+ } else if (cs->word_len <= 16) {
+ width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ es = 2;
+ } else {
+ width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ es = 4;
+ }
+
+ memset(&cfg, 0, sizeof(cfg));
+ cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
+ cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
+ cfg.src_addr_width = width;
+ cfg.dst_addr_width = width;
+ cfg.src_maxburst = 1;
+ cfg.dst_maxburst = 1;
+
+ rx = xfer->rx_buf;
+ tx = xfer->tx_buf;
+
+ count = xfer->len;
+
+ if (tx != NULL)
+ omap2_mcspi_tx_dma(spi, xfer, cfg);
+
+ if (rx != NULL)
+ return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
+
return count;
}
return ret;
}
- ret = omap2_mcspi_enable_clocks(mcspi);
+ ret = pm_runtime_get_sync(mcspi->dev);
if (ret < 0)
return ret;
ret = omap2_mcspi_setup_transfer(spi, NULL);
- omap2_mcspi_disable_clocks(mcspi);
+ pm_runtime_mark_last_busy(mcspi->dev);
+ pm_runtime_put_autosuspend(mcspi->dev);
return ret;
}
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
int ret = 0;
- ret = omap2_mcspi_enable_clocks(mcspi);
+ ret = pm_runtime_get_sync(mcspi->dev);
if (ret < 0)
return ret;
ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
omap2_mcspi_set_master_mode(master);
- omap2_mcspi_disable_clocks(mcspi);
+ pm_runtime_mark_last_busy(mcspi->dev);
+ pm_runtime_put_autosuspend(mcspi->dev);
return 0;
}
static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
{
struct spi_master *master;
- struct omap2_mcspi_platform_config *pdata;
+ const struct omap2_mcspi_platform_config *pdata;
struct omap2_mcspi *mcspi;
struct resource *r;
int status = 0, i;
static int bus_num = 1;
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
+ struct pinctrl *pinctrl;
master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
if (master == NULL) {
if (status < 0)
goto dma_chnl_free;
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+ dev_warn(&pdev->dev,
+ "pins are not configured from the driver\n");
+
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
pm_runtime_enable(&pdev->dev);
kfree(mcspi->dma_channels);
free_master:
spi_master_put(master);
- platform_set_drvdata(pdev, NULL);
return status;
}
mcspi = spi_master_get_devdata(master);
dma_channels = mcspi->dma_channels;
- omap2_mcspi_disable_clocks(mcspi);
+ pm_runtime_put_sync(mcspi->dev);
pm_runtime_disable(&pdev->dev);
spi_unregister_master(master);
kfree(dma_channels);
- platform_set_drvdata(pdev, NULL);
return 0;
}
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
struct omap2_mcspi_cs *cs;
- omap2_mcspi_enable_clocks(mcspi);
+ pm_runtime_get_sync(mcspi->dev);
list_for_each_entry(cs, &ctx->cs, node) {
if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
/*
* We need to toggle CS state for OMAP take this
* change in account.
*/
- MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
+ cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
- MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
+ cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
}
}
- omap2_mcspi_disable_clocks(mcspi);
+ pm_runtime_mark_last_busy(mcspi->dev);
+ pm_runtime_put_autosuspend(mcspi->dev);
return 0;
}
#else
projects / linux.git / commitdiff