fpga: fix spelling mistakes

Run the fpga subsystem through aspell.

Signed-off-by: Tom Rix <[email protected]>
Reviewed-by: Fernando Pacheco <[email protected]>
Signed-off-by: Moritz Fischer <[email protected]>

diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 75df90d1e54c0b2e8c993777a373d82a2ca94c0d..ef9eec71f6f3afa648af6df818d847b4fa21ed3d 100644 (file)
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -10,7 +10,7 @@ Authors:
 - Xu Yilun <[email protected]>
 
 The Device Feature List (DFL) FPGA framework (and drivers according to
-this framework) hides the very details of low layer hardwares and provides
+this framework) hides the very details of low layer hardware and provides
 unified interfaces to userspace. Applications could use these interfaces to
 configure, enumerate, open and access FPGA accelerators on platforms which
 implement the DFL in the device memory. Besides this, the DFL framework
@@ -205,7 +205,7 @@ given Device Feature Lists and create platform devices for feature devices
 also abstracts operations for the private features and exposes common ops to
 feature device drivers.
 
-The FPGA DFL Device could be different hardwares, e.g. PCIe device, platform
+The FPGA DFL Device could be different hardware, e.g. PCIe device, platform
 device and etc. Its driver module is always loaded first once the device is
 created by the system. This driver plays an infrastructural role in the
 driver architecture. It locates the DFLs in the device memory, handles them

diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 4e0edb60bfba6ae8c8f8f8fa7f6656feca098bb6..ccf4546eff297efc45e616b43f88281ca1675d3d 100644 (file)
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/altera-cvp.c
@@ -346,7 +346,7 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
        }
 
        if (val & VSE_CVP_STATUS_CFG_RDY) {
-               dev_warn(&mgr->dev, "CvP already started, teardown first\n");
+               dev_warn(&mgr->dev, "CvP already started, tear down first\n");
                ret = altera_cvp_teardown(mgr, info);
                if (ret)
                        return ret;

diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 1194c0e850e074b2a11b015abda75807b7090195..d61ce9a1887929c11234c8d2e5953aaf69086bfb 100644 (file)
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -148,7 +148,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
 
        /*
         * it allows userspace to reset the PR region's logic by disabling and
-        * reenabling the bridge to clear things out between accleration runs.
+        * reenabling the bridge to clear things out between acceleration runs.
         * so no need to hold the bridges after partial reconfiguration.
         */
        if (region->get_bridges)

diff --git a/drivers/fpga/dfl-n3000-nios.c b/drivers/fpga/dfl-n3000-nios.c
index 7a95366f6516f87ddb93be06e514e290d893c2ee..9ddf1d1d392f353aa4a704fd58695d07985dd338 100644 (file)
--- a/drivers/fpga/dfl-n3000-nios.c
+++ b/drivers/fpga/dfl-n3000-nios.c
@@ -461,7 +461,7 @@ static int n3000_nios_poll_stat_timeout(void __iomem *base, u64 *v)
         * We don't use the time based timeout here for performance.
         *
         * The regbus read/write is on the critical path of Intel PAC N3000
-        * image programing. The time based timeout checking will add too much
+        * image programming. The time based timeout checking will add too much
         * overhead on it. Usually the state changes in 1 or 2 loops on the
         * test server, and we set 10000 times loop here for safety.
         */

diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 2b82c96ba56c76df11c71a4561f2dcc0f9be773e..dac9c3d45e6c34478e95ab6ae6d15a0745f8fd8d 100644 (file)
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -232,7 +232,7 @@ struct dfl_feature_irq_ctx {
  * @id: sub feature id.
  * @resource_index: each sub feature has one mmio resource for its registers.
  *                 this index is used to find its mmio resource from the
- *                 feature dev (platform device)'s reources.
+ *                 feature dev (platform device)'s resources.
  * @ioaddr: mapped mmio resource address.
  * @irq_ctx: interrupt context list.
  * @nr_irqs: number of interrupt contexts.

diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c
index 2bfb2ff86930555c1638610726caeb18690fa31e..b09f68f8e1b06f0623bbe2980a59f44ade8ed343 100644 (file)
--- a/drivers/fpga/fpga-bridge.c
+++ b/drivers/fpga/fpga-bridge.c
@@ -230,7 +230,7 @@ EXPORT_SYMBOL_GPL(fpga_bridges_put);
  *
  * Get an exclusive reference to the bridge and and it to the list.
  *
- * Return 0 for success, error code from of_fpga_bridge_get() othewise.
+ * Return 0 for success, error code from of_fpga_bridge_get() otherwise.
  */
 int of_fpga_bridge_get_to_list(struct device_node *np,
                               struct fpga_image_info *info,
@@ -260,7 +260,7 @@ EXPORT_SYMBOL_GPL(of_fpga_bridge_get_to_list);
  *
  * Get an exclusive reference to the bridge and and it to the list.
  *
- * Return 0 for success, error code from fpga_bridge_get() othewise.
+ * Return 0 for success, error code from fpga_bridge_get() otherwise.
  */
 int fpga_bridge_get_to_list(struct device *dev,
                            struct fpga_image_info *info,

diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 07fa8d9ec67500586878267c2cd7ee541ceeeefd..9b75bd4f93d8e0351193a6bda9d01a3e06fd6328 100644 (file)
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -192,7 +192,7 @@ static void zynq_step_dma(struct zynq_fpga_priv *priv)
 
        /* Once the first transfer is queued we can turn on the ISR, future
         * calls to zynq_step_dma will happen from the ISR context. The
-        * dma_lock spinlock guarentees this handover is done coherently, the
+        * dma_lock spinlock guarantees this handover is done coherently, the
         * ISR enable is put at the end to avoid another CPU spinning in the
         * ISR on this lock.
         */
@@ -267,7 +267,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
                ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
                if (!(ctrl & CTRL_SEC_EN_MASK)) {
                        dev_err(&mgr->dev,
-                               "System not secure, can't use crypted bitstreams\n");
+                               "System not secure, can't use encrypted bitstreams\n");
                        err = -EINVAL;
                        goto out_err;
                }
@@ -344,7 +344,7 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
 
        /* set configuration register with following options:
         * - enable PCAP interface
-        * - set throughput for maximum speed (if bistream not crypted)
+        * - set throughput for maximum speed (if bistream not encrypted)
         * - set CPU in user mode
         */
        ctrl = zynq_fpga_read(priv, CTRL_OFFSET);

diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index ec2cd8bfceb00a8f484b6e976c95a2baf922ce45..474c1f50630707461ed7e57794f9df28ccfec059 100644 (file)
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -110,7 +110,7 @@ struct fpga_image_info {
  * @initial_header_size: Maximum number of bytes that should be passed into write_init
  * @state: returns an enum value of the FPGA's state
  * @status: returns status of the FPGA, including reconfiguration error code
- * @write_init: prepare the FPGA to receive confuration data
+ * @write_init: prepare the FPGA to receive configuration data
  * @write: write count bytes of configuration data to the FPGA
  * @write_sg: write the scatter list of configuration data to the FPGA
  * @write_complete: set FPGA to operating state after writing is done