net: phy: marvell10g: Don't explicitly set Pause and Asym_Pause

The PHY core expects PHY drivers not to set Pause and Asym_Pause bits,
unless the driver only wants to specify one of them due to HW
limitation. In the case of the Marvell10g driver, we don't need to set
them.

Signed-off-by: Maxime Chevallier <[email protected]>
Suggested-by: Andrew Lunn <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index b83eb19cf8bb94227f03546e43ba1b1906f934fb..f9e0a2fc0277503560ed64662dafbfe1fce1bf55 100644 (file)
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -242,9 +242,6 @@ static int mv3310_config_init(struct phy_device *phydev)
            phydev->interface != PHY_INTERFACE_MODE_10GKR)
                return -ENODEV;
 
-       __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
-       __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
-
        if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
                val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
                if (val < 0)