ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register

DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
correct frequency of LRCLK and BCLK. Sometimes the read-only value
can't be updated timely after enabling SYSCLK. This results in wrong
calculation values. Delay is introduced here to wait for newest value
from register. The time of the delay should be at least 500~1000us
according to test.

Signed-off-by: Chancel Liu <[email protected]>
Acked-by: Charles Keepax <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index b4b4355c6728b0c4977bcd3f0b24006561c432bf..b901e4c65e8a508c370f8ef5ced11a9c6639275e 100644 (file)
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -2503,6 +2503,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component)
                snd_soc_component_update_bits(component, WM8962_CLOCKING2,
                                WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
 
+       /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
+        * correct frequency of LRCLK and BCLK. Sometimes the read-only value
+        * can't be updated timely after enabling SYSCLK. This results in wrong
+        * calculation values. Delay is introduced here to wait for newest
+        * value from register. The time of the delay should be at least
+        * 500~1000us according to test.
+        */
+       usleep_range(500, 1000);
        dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
 
        if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)