Merge tag 'drm-msm-fixes-2023-03-09' of https://gitlab.freedesktop.org/drm/msm into...

msm-fixes for v6.3-rc2

- Fix for possible invalid ptr free in submit ioctl syncobj cleanup path.
- Synchronize GMU removal in driver teardown path
- a5xx preemption fixes
- Fix runpm imbalance at unbind
- DPU hw catalog fixes:
 - set DPU_MDP_PERIPH_0_REMOVED for sc8280xp as this is another chipset
   where the PERIPH_0 block of registers is not there
 - fix the DPU features supported in QCM2290 by comparing it with the
   downstream device tree
 - fix the length of registers in the sc7180_ctl from 0xe4 to 0x1dc
 - fix the max mixer line width for sm6115 and qcm2290 chipsets in the
   DPU catalog
 - fix the scaler version on sm8550, sc8280xp, sm8450, sm8250, sm8350
   and sm6115. This was incorrectly populated on the SW version of the
   scaler library and  not the scaler HW version
 - Drop dim layer support for msm8998 as its not indicated to be
   supported in the downstream DTSI
 - fix the DPU_CLK_CTRL bits for msm 8998 sspp blocks
 - Use DPU_CLK_CTRL_DMA* prefix instead of DPU_CLK_CTRL_CURSOR*
   for all chipsets for the DMA sspp blocks
 - fix the ping-pong block base address for sc7280 in the DPU HW catalog
- Fix stack corruption issue in the dpu_hw_ctl_setup_blendstage() function
  as it was causing a negative left shift by protecting against an invalid
  index
- Clear the DSPP reservations in dpu_rm_release(). This was missed out and
  as as result the DSPP was not released from the resource manager global
  state.

Signed-off-by: Dave Airlie <[email protected]>
From: Rob Clark <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvH+VH_Wx3mFMG51CMnoiU06CM-+-WMhM73M42Qx7Bp4A@mail.gmail.com

diff --combined drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index d09221f97f71c38f64b38b5fe12a55ddfb95bc64,047c5e8c87ff45c97063f1d9b7c5f22393d03d1f..a1e006ec5dcec2eaa5c72d34d06d31e4f0ba1308
--- 1/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
--- 2/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@@ -5,7 -5,7 +5,7 @@@
  #include <linux/kernel.h>
  #include <linux/types.h>
  #include <linux/cpumask.h>
 -#include <linux/qcom_scm.h>
 +#include <linux/firmware/qcom/qcom_scm.h>
  #include <linux/pm_opp.h>
  #include <linux/nvmem-consumer.h>
  #include <linux/slab.h>
@@@ -151,8 -151,8 +151,8 @@@ static void a5xx_submit(struct msm_gpu 
        OUT_RING(ring, 1);
  
        /* Enable local preemption for finegrain preemption */
-       OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
-       OUT_RING(ring, 0x02);
+       OUT_PKT7(ring, CP_PREEMPT_ENABLE_LOCAL, 1);
+       OUT_RING(ring, 0x1);
  
        /* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */
        OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
@@@ -806,7 -806,7 +806,7 @@@ static int a5xx_hw_init(struct msm_gpu 
        gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
  
        /* Set the highest bank bit */
-       if (adreno_is_a540(adreno_gpu))
+       if (adreno_is_a540(adreno_gpu) || adreno_is_a530(adreno_gpu))
                regbit = 2;
        else
                regbit = 1;