Merge branch 'arm/renesas' into arm/smmu

diff --cc drivers/iommu/ipmmu-vmsa.c
index 12bcb95bdaa83fc486e50bb280daf6b844a11eef,408ad0b2591925e02291bc8b51b0644c633f00c5..ad0098c0c87c7544f18b70c0bd9dc43913ca0478
--- 1/drivers/iommu/ipmmu-vmsa.c
--- 2/drivers/iommu/ipmmu-vmsa.c
+++ b/drivers/iommu/ipmmu-vmsa.c
@@@ -495,7 -459,54 +459,55 @@@ static void ipmmu_domain_setup_context(
         */
        ipmmu_ctx_write_all(domain, IMCTR,
                            IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
+ }
+ 
+ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
+ {
+       int ret;
+ 
+       /*
+        * Allocate the page table operations.
+        *
+        * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
+        * access, Long-descriptor format" that the NStable bit being set in a
+        * table descriptor will result in the NStable and NS bits of all child
+        * entries being ignored and considered as being set. The IPMMU seems
+        * not to comply with this, as it generates a secure access page fault
+        * if any of the NStable and NS bits isn't set when running in
+        * non-secure mode.
+        */
+       domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
+       domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
+       domain->cfg.ias = 32;
+       domain->cfg.oas = 40;
+       domain->cfg.tlb = &ipmmu_gather_ops;
+       domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
+       domain->io_domain.geometry.force_aperture = true;
+       /*
+        * TODO: Add support for coherent walk through CCI with DVM and remove
+        * cache handling. For now, delegate it to the io-pgtable code.
+        */
++      domain->cfg.coherent_walk = false;
+       domain->cfg.iommu_dev = domain->mmu->root->dev;
+ 
+       /*
+        * Find an unused context.
+        */
+       ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
+       if (ret < 0)
+               return ret;
+ 
+       domain->context_id = ret;
+ 
+       domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
+                                          domain);
+       if (!domain->iop) {
+               ipmmu_domain_free_context(domain->mmu->root,
+                                         domain->context_id);
+               return -EINVAL;
+       }
  
+       ipmmu_domain_setup_context(domain);
        return 0;
  }