Merge tag 'drm-intel-next-2020-08-24-1' of git://anongit.freedesktop.org/drm/drm...

UAPI Changes:

- Introduce a mechanism to extend execbuf2 (Lionel)
- Add syncobj timeline support (Lionel)

Driver Changes:

- Limit stolen mem usage on the compressed frame buffer (Ville)
- Some clean-up around display's cdclk (Ville)
- Some DDI changes for better DP link training according
  to spec (Imre)
- Provide the perf pmu.module (Chris)
- Remove dobious Valleyview PCI IDs (Alexei)
- Add new display power saving feature for gen12+ called
  HOBL (Jose)
- Move SKL's clock gating w/a to skl_init_clock_gating() (Ville)
- Rocket Lake display additions (Matt)
- Selftest: temporarily downgrade on severity of frequency
            scaling tests (Chris)
- Introduce a new display workaround for fixing FLR related
  issues on new PCH. (Jose)
- Temporarily disable FBC on TGL. It was the culprit of random
  underruns. (Uma).
- Copy default modparams to mock i915_device (Chris)
- Add compiler paranoia for checking HWSP values (Chris)
- Remove useless gen check before calling intel_rps_boost (Chris)
- Fix a null pointer dereference (Chris)
- Add a couple of missing i915_active_fini() (Chris)
- Update TGL display power's bw_buddy table according to
  update spec (Matt)
- Fix couple wrong return values (Tianjia)
- Selftest: Avoid passing random 0 into ilog2 (George)
- Many Tiger Lake display fixes and improvements for Type-C and
  DP compliance (Imre, Jose)
- Start the addition of PSR2 selective fetch (Jose)
- Update a few DMC and HuC firmware versions (Jose)
- Add gen11+ w/a to fix underuns (Matt)
- Fix cmd parser desc matching with mask (Mika)

Signed-off-by: Dave Airlie <[email protected]>
From: Rodrigo Vivi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --combined drivers/gpu/drm/i915/display/intel_fbc.c
index 24c3a0f212c66103db3a61cd0f3ac99ddd3d1fe6,195b8be4532af4a2aeafbe8810d1dc530c38868b..135f5e8a4d70d57bee3f39151c5cd9870510ac52
--- 1/drivers/gpu/drm/i915/display/intel_fbc.c
--- 2/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@@ -424,6 -424,14 +424,14 @@@ static void intel_fbc_deactivate(struc
        fbc->no_fbc_reason = reason;
  }
  
+ static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
+ {
+       if (INTEL_GEN(i915) >= 5 || IS_G4X(i915))
+               return BIT_ULL(28);
+       else
+               return BIT_ULL(32);
+ }
+ 
  static int find_compression_threshold(struct drm_i915_private *dev_priv,
                                      struct drm_mm_node *node,
                                      unsigned int size,
@@@ -442,6 -450,8 +450,8 @@@
        else
                end = U64_MAX;
  
+       end = min(end, intel_fbc_cfb_base_max(dev_priv));
+ 
        /* HACK: This code depends on what we will do in *_enable_fbc. If that
         * code changes, this code needs to change as well.
         *
@@@ -477,7 -487,7 +487,7 @@@ static int intel_fbc_alloc_cfb(struct d
                               unsigned int size, unsigned int fb_cpp)
  {
        struct intel_fbc *fbc = &dev_priv->fbc;
 -      struct drm_mm_node *uninitialized_var(compressed_llb);
 +      struct drm_mm_node *compressed_llb;
        int ret;
  
        drm_WARN_ON(&dev_priv->drm,
@@@ -1416,6 -1426,13 +1426,13 @@@ static int intel_sanitize_fbc_option(st
        if (!HAS_FBC(dev_priv))
                return 0;
  
+       /*
+        * Fbc is causing random underruns in CI execution on TGL platforms.
+        * Disabling the same while the problem is being debugged and analyzed.
+        */
+       if (IS_TIGERLAKE(dev_priv))
+               return 0;
+ 
        if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
                return 1;
  

diff --combined drivers/gpu/drm/i915/gt/intel_lrc.c
index 24322ef08aa40e3d5cb368cd7136445908fe3094,94d8c9d76a26017c13fb72db4b3bae92a8f2978a..d03da2f64a49d868ed9aafbcecd8907526a5d62e
--- 1/drivers/gpu/drm/i915/gt/intel_lrc.c
--- 2/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@@ -1106,7 -1106,7 +1106,7 @@@ static struct i915_request 
  __unwind_incomplete_requests(struct intel_engine_cs *engine)
  {
        struct i915_request *rq, *rn, *active = NULL;
 -      struct list_head *uninitialized_var(pl);
 +      struct list_head *pl;
        int prio = I915_PRIORITY_INVALID;
  
        lockdep_assert_held(&engine->active.lock);
@@@ -4555,7 -4555,7 +4555,7 @@@ static int gen8_emit_flush_render(struc
                        vf_flush_wa = true;
  
                /* WaForGAMHang:kbl */
-               if (IS_KBL_REVID(request->engine->i915, 0, KBL_REVID_B0))
+               if (IS_KBL_GT_REVID(request->engine->i915, 0, KBL_REVID_B0))
                        dc_flush_wa = true;
        }