drm/amd/amdgpu: Enable scratch data dump for mes 12

MES internal will check CP_MES_MSCRATCH_LO/HI register to set scratch
data location during ucode start, driver side need to start the MES
one by one with different setting for each pipe

Signed-off-by: Shaoyun Liu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index c6f93cbd6739f064ab70a434b754b8a09d85ef2c..2df2444ee892cd1d8cac7efc97c886e57ed28db8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -40,7 +40,7 @@
 #define AMDGPU_MES_VERSION_MASK                0x00000fff
 #define AMDGPU_MES_API_VERSION_MASK    0x00fff000
 #define AMDGPU_MES_FEAT_VERSION_MASK   0xff000000
-#define AMDGPU_MES_MSCRATCH_SIZE       0x8000
+#define AMDGPU_MES_MSCRATCH_SIZE       0x40000
 
 enum amdgpu_mes_priority_level {
        AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 5b537806b4da640ef6e53b3488afa47ed3dbaf57..901e924e69ad94813c64abccfcc3d0101132c641 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -756,7 +756,8 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
 
        if (amdgpu_mes_log_enable) {
                mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
-               mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr + pipe * AMDGPU_MES_LOG_BUFFER_SIZE;
+               mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr +
+                               pipe * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);
        }
 
        if (enforce_isolation)
@@ -983,29 +984,50 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
        uint32_t pipe, data = 0;
 
        if (enable) {
-               data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
-               WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
-
                mutex_lock(&adev->srbm_mutex);
                for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
                        soc21_grbm_select(adev, 3, pipe, 0, 0);
+                       if (amdgpu_mes_log_enable) {
+                               u32 log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE;
+                               /* In case uni mes is not enabled, only program for pipe 0 */
+                               if (adev->mes.event_log_size >= (pipe + 1) * log_size) {
+                                       WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO,
+                                                    lower_32_bits(adev->mes.event_log_gpu_addr +
+                                                    pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
+                                       WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI,
+                                                    upper_32_bits(adev->mes.event_log_gpu_addr +
+                                                    pipe * log_size + AMDGPU_MES_LOG_BUFFER_SIZE));
+                                       dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n",
+                                                RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),
+                                                RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));
+                               }
+                       }
+
+                       data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
+                       if (pipe == 0)
+                               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
+                       else
+                               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);
+                       WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 
                        ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
                        WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
                                     lower_32_bits(ucode_addr));
                        WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
                                     upper_32_bits(ucode_addr));
+
+                       /* unhalt MES and activate one pipe each loop */
+                       data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
+                       if (pipe)
+                               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
+                       dev_info(adev->dev, "program CP_MES_CNTL : 0x%x\n", data);
+
+                       WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
+
                }
                soc21_grbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
 
-               /* unhalt MES and activate pipe0 */
-               data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
-               data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);
-               WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
-
                if (amdgpu_emu_mode)
                        msleep(100);
                else if (adev->enable_uni_mes)
@@ -1479,8 +1501,9 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
        adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
        adev->mes.enable_legacy_queue_map = true;
 
-       adev->mes.event_log_size = adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE) : AMDGPU_MES_LOG_BUFFER_SIZE;
-
+       adev->mes.event_log_size = adev->enable_uni_mes ?
+               (AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :
+               (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE);
        r = amdgpu_mes_init(adev);
        if (r)
                return r;