perf/x86: Allow for 8<num_fixed_counters<16

The 64 bit value read from MSR_ARCH_PERFMON_FIXED_CTR_CTRL is being
bit-wise masked with the value (0x03 << i*4). However, the shifted value
is evaluated using 32 bit arithmetic, so will UB when i > 8. Fix this
by making 0x03 a ULL so that the shift is performed using 64 bit
arithmetic.

This makes the arithmetic internally consistent and preparers for the
day when hardware provides 8<num_fixed_counters<16.

Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 3fe66b7aa7214fc11f3fafc40a1689a6a970a443..c7fcc8d79f01fc791b122b3e7d5599dd92f35614 100644 (file)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -278,7 +278,7 @@ bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
                for (i = 0; i < num_counters_fixed; i++) {
                        if (fixed_counter_disabled(i, pmu))
                                continue;
-                       if (val & (0x03 << i*4)) {
+                       if (val & (0x03ULL << i*4)) {
                                bios_fail = 1;
                                val_fail = val;
                                reg_fail = reg;