ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA

Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 622cc7cc1471b81079744e26be0c9c1e8c8a4ae6..a060718758b6755a154c1842f95301d1a8c93806 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -96,10 +96,14 @@
                        rxd1-skew-ps = <0>;
                        rxd2-skew-ps = <0>;
                        rxd3-skew-ps = <0>;
+                       txd0-skew-ps = <0>;
+                       txd1-skew-ps = <0>;
+                       txd2-skew-ps = <0>;
+                       txd3-skew-ps = <0>;
                        txen-skew-ps = <0>;
-                       txc-skew-ps = <2600>;
+                       txc-skew-ps = <1860>;
                        rxdv-skew-ps = <0>;
-                       rxc-skew-ps = <2000>;
+                       rxc-skew-ps = <1860>;
                };
        };
 };