--- /dev/null
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+#ifndef _XE_BARS_H_
+#define _XE_BARS_H_
+
+#define GTTMMADR_BAR 0 /* MMIO + GTT */
+#define LMEM_BAR 2 /* VRAM */
+
+#endif
#include <drm/drm_managed.h>
#include <drm/xe_drm.h>
+#include "regs/xe_bars.h"
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_regs.h"
* registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
*/
xe->mmio.size = pci_resource_len(pdev, mmio_bar);
- xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
+ xe->mmio.regs = pci_iomap(pdev, mmio_bar, GTTMMADR_BAR);
if (xe->mmio.regs == NULL) {
drm_err(&xe->drm, "failed to map registers\n");
return -EIO;