]> Git Repo - linux.git/commitdiff
cxl/registers: Fix Documentation warning
authorDan Williams <[email protected]>
Sat, 4 Sep 2021 02:21:06 +0000 (19:21 -0700)
committerDan Williams <[email protected]>
Tue, 7 Sep 2021 18:39:02 +0000 (11:39 -0700)
Commit 0f06157e0135 ("cxl/core: Move register mapping infrastructure")
neglected to add a DOC header for the new drivers/core/regs.c file.

Reported-by: Ben Widawsky <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Link: https://lore.kernel.org/r/163072206675.2250120.3527179192933919995.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <[email protected]>
Documentation/driver-api/cxl/memory-devices.rst
drivers/cxl/core/regs.c

index df799cdf1c3fa8b985da27d8795aed821b38863d..50ebcda17ad056aa3a168d00d057107cc3ee0438 100644 (file)
@@ -43,7 +43,7 @@ CXL Core
    :doc: cxl pmem
 
 .. kernel-doc:: drivers/cxl/core/regs.c
-   :internal:
+   :doc: cxl registers
 
 External Interfaces
 ===================
index 8535a7b94f28cacae292389e14bb0ea8f1cd8a15..41de4a136ecd71af23fb72da26ac5fc3208c2fbc 100644 (file)
@@ -1,12 +1,25 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright(c) 2020 Intel Corporation. */
-
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/device.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <cxlmem.h>
 
+/**
+ * DOC: cxl registers
+ *
+ * CXL device capabilities are enumerated by PCI DVSEC (Designated
+ * Vendor-specific) and / or descriptors provided by platform firmware.
+ * They can be defined as a set like the device and component registers
+ * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
+ * Extended Capabilities, or they can be individual capabilities
+ * appended to bridged and endpoint devices.
+ *
+ * Provide common infrastructure for enumerating and mapping these
+ * discrete capabilities.
+ */
+
 /**
  * cxl_probe_component_regs() - Detect CXL Component register blocks
  * @dev: Host device of the @base mapping
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