drm/amdgpu: Use dev_ prints for virtualization as it supports multi adapter

So we can get clearer per device logging.

Signed-off-by: Vignesh Chander <[email protected]>
Reviewed-by: Zhigang Luo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 6b71ee85ee65562ec3d8b6a6c9cc9b5584c67051..65656afc6ed1c2055d4e22a23708d8477d6e6695 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -93,7 +93,7 @@ static int xgpu_ai_poll_ack(struct amdgpu_device *adev)
                timeout -= 5;
        } while (timeout > 1);
 
-       pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);
+       dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);
 
        return -ETIME;
 }
@@ -111,7 +111,7 @@ static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
                timeout -= 10;
        } while (timeout > 1);
 
-       pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
+       dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);
 
        return -ETIME;
 }
@@ -132,7 +132,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
                xgpu_ai_mailbox_set_valid(adev, false);
                trn = xgpu_ai_peek_ack(adev);
                if (trn) {
-                       pr_err("trn=%x ACK should not assert! wait again !\n", trn);
+                       dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn);
                        msleep(1);
                }
        } while(trn);
@@ -155,7 +155,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
        /* start to poll ack */
        r = xgpu_ai_poll_ack(adev);
        if (r)
-               pr_err("Doesn't get ack from pf, continue\n");
+               dev_err(adev->dev, "Doesn't get ack from pf, continue\n");
 
        xgpu_ai_mailbox_set_valid(adev, false);
 }
@@ -173,7 +173,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
                req == IDH_REQ_GPU_RESET_ACCESS) {
                r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
                if (r) {
-                       pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
+                       dev_err(adev->dev, "Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
                        return r;
                }
                /* Retrieve checksum from mailbox2 */
@@ -231,7 +231,7 @@ static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *source,
                                        struct amdgpu_iv_entry *entry)
 {
-       DRM_DEBUG("get ack intr and do nothing.\n");
+       dev_dbg(adev->dev, "get ack intr and do nothing.\n");
        return 0;
 }
 
@@ -258,12 +258,15 @@ static int xgpu_ai_wait_reset(struct amdgpu_device *adev)
 {
        int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;
        do {
-               if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
+               if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {
+                       dev_dbg(adev->dev, "Got AI IDH_FLR_NOTIFICATION_CMPL after %d ms\n", AI_MAILBOX_POLL_FLR_TIMEDOUT - timeout);
                        return 0;
+               }
                msleep(10);
                timeout -= 10;
        } while (timeout > 1);
-       dev_warn(adev->dev, "waiting IDH_FLR_NOTIFICATION_CMPL timeout\n");
+
+       dev_dbg(adev->dev, "waiting AI IDH_FLR_NOTIFICATION_CMPL timeout\n");
        return -ETIME;
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index 22af30a15a5fd7aea5040bfb63a7bbe9ab9ce6e3..17e1e8cc243752a0a31d03770e996f92d53628c1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -91,7 +91,7 @@ static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
                timeout -= 5;
        } while (timeout > 1);
 
-       pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", NV_MAILBOX_POLL_ACK_TIMEDOUT);
+       dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec \n", NV_MAILBOX_POLL_ACK_TIMEDOUT);
 
        return -ETIME;
 }
@@ -106,13 +106,16 @@ static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
 
        do {
                r = xgpu_nv_mailbox_rcv_msg(adev, event);
-               if (!r)
+               if (!r) {
+                       dev_dbg(adev->dev, "rcv_msg 0x%x after %llu ms\n", event, NV_MAILBOX_POLL_MSG_TIMEDOUT - timeout + now);
                        return 0;
+               }
 
                msleep(10);
                now = (uint64_t)ktime_to_ms(ktime_get());
        } while (timeout > now);
 
+       dev_dbg(adev->dev, "nv_poll_msg timed out\n");
 
        return -ETIME;
 }
@@ -133,11 +136,12 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
                xgpu_nv_mailbox_set_valid(adev, false);
                trn = xgpu_nv_peek_ack(adev);
                if (trn) {
-                       pr_err("trn=%x ACK should not assert! wait again !\n", trn);
+                       dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn);
                        msleep(1);
                }
        } while (trn);
 
+       dev_dbg(adev->dev, "trans_msg req = 0x%x, data1 = 0x%x\n", req, data1);
        WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);
        WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);
        WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);
@@ -147,7 +151,7 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
        /* start to poll ack */
        r = xgpu_nv_poll_ack(adev);
        if (r)
-               pr_err("Doesn't get ack from pf, continue\n");
+               dev_err(adev->dev, "Doesn't get ack from pf, continue\n");
 
        xgpu_nv_mailbox_set_valid(adev, false);
 }
@@ -185,7 +189,7 @@ send_request:
                                goto send_request;
 
                        if (req != IDH_REQ_GPU_INIT_DATA) {
-                               pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
+                               dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r);
                                return r;
                        } else /* host doesn't support REQ_GPU_INIT_DATA handshake */
                                adev->virt.req_init_data_ver = 0;
@@ -261,7 +265,7 @@ static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *source,
                                        struct amdgpu_iv_entry *entry)
 {
-       DRM_DEBUG("get ack intr and do nothing.\n");
+       dev_dbg(adev->dev, "get ack intr and do nothing.\n");
        return 0;
 }
 
@@ -291,12 +295,15 @@ static int xgpu_nv_wait_reset(struct amdgpu_device *adev)
 {
        int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;
        do {
-               if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
+               if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) {
+                       dev_dbg(adev->dev, "Got NV IDH_FLR_NOTIFICATION_CMPL after %d ms\n", NV_MAILBOX_POLL_FLR_TIMEDOUT - timeout);
                        return 0;
+               }
                msleep(10);
                timeout -= 10;
        } while (timeout > 1);
-       dev_warn(adev->dev, "waiting IDH_FLR_NOTIFICATION_CMPL timeout\n");
+
+       dev_dbg(adev->dev, "waiting NV IDH_FLR_NOTIFICATION_CMPL timeout\n");
        return -ETIME;
 }