ARM: dts: fix L2 address in Hi3620

Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: Haojian Zhuang <[email protected]>
Acked-by: Wei Xu <[email protected]>
Cc: [email protected]
Signed-off-by: Arnd Bergmann <[email protected]>

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index ab1116d086be82bc405f599cd3f2677a749fae42..83a5b8685bd961818bfa8c9d6bea6bc3bff4ff24 100644 (file)
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -73,7 +73,7 @@
 
                L2: l2-cache {
                        compatible = "arm,pl310-cache";
-                       reg = <0xfc10000 0x100000>;
+                       reg = <0x100000 0x100000>;
                        interrupts = <0 15 4>;
                        cache-unified;
                        cache-level = <2>;