dt-bindings: opp: Allow empty OPP tables

Currently the optional property opp-shared is used within an opp table
to tell that a set of devices share their clock/voltage lines (and the
OPP points).
It is therefore possible to use an empty OPP table to convey only that
information, useful in situations where the opp points are provided via
other means (hardware. firmware, etc).

Update the documentation to remark this additional case and provide an
example.

Signed-off-by: Nicola Mazzucato <[email protected]>
Signed-off-by: Viresh Kumar <[email protected]>

diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt
index 9847dfeeffcba0bb4423c0418e4007760be00f96..08b3da4736cf29afa0927ff9706cc23cab0eb5ed 100644 (file)
--- a/Documentation/devicetree/bindings/opp/opp.txt
+++ b/Documentation/devicetree/bindings/opp/opp.txt
@@ -65,7 +65,9 @@ Required properties:
 
 - OPP nodes: One or more OPP nodes describing voltage-current-frequency
   combinations. Their name isn't significant but their phandle can be used to
-  reference an OPP.
+  reference an OPP. These are mandatory except for the case where the OPP table
+  is present only to indicate dependency between devices using the opp-shared
+  property.
 
 Optional properties:
 - opp-shared: Indicates that device nodes using this OPP Table Node's phandle
@@ -568,3 +570,53 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
                };
        };
 };
+
+Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
+distinct clock controls but two sets of clock/voltage/current lines.
+
+/ {
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x100>;
+                       next-level-cache = <&A53_L2>;
+                       clocks = <&dvfs_controller 0>;
+                       operating-points-v2 = <&cpu_opp0_table>;
+               };
+               cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x101>;
+                       next-level-cache = <&A53_L2>;
+                       clocks = <&dvfs_controller 1>;
+                       operating-points-v2 = <&cpu_opp0_table>;
+               };
+               cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x102>;
+                       next-level-cache = <&A53_L2>;
+                       clocks = <&dvfs_controller 2>;
+                       operating-points-v2 = <&cpu_opp1_table>;
+               };
+               cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x103>;
+                       next-level-cache = <&A53_L2>;
+                       clocks = <&dvfs_controller 3>;
+                       operating-points-v2 = <&cpu_opp1_table>;
+               };
+
+       };
+
+       cpu_opp0_table: opp0_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+       };
+
+       cpu_opp1_table: opp1_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+       };
+};