Merge tag 'riscv-for-linus-6.14-mw1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - The PH1520 pinctrl and dwmac drivers are enabeled in defconfig

 - A redundant AQRL barrier has been removed from the futex cmpxchg
   implementation

 - Support for the T-Head vector extensions, which includes exposing
   these extensions to userspace on systems that implement them

 - Some more page table information is now printed on die() and systems
   that cause PA overflows

* tag 'riscv-for-linus-6.14-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: add a warning when physical memory address overflows
  riscv/mm/fault: add show_pte() before die()
  riscv: Add ghostwrite vulnerability
  selftests: riscv: Support xtheadvector in vector tests
  selftests: riscv: Fix vector tests
  riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
  riscv: hwprobe: Add thead vendor extension probing
  riscv: vector: Support xtheadvector save/restore
  riscv: Add xtheadvector instruction definitions
  riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
  RISC-V: define the elements of the VCSR vector CSR
  riscv: vector: Use vlenb from DT for thead
  riscv: Add thead and xtheadvector as a vendor extension
  riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
  dt-bindings: cpus: add a thead vlen register length property
  dt-bindings: riscv: Add xtheadvector ISA extension description
  RISC-V: Mark riscv_v_init() as __init
  riscv: defconfig: drop RT_GROUP_SCHED=y
  riscv/futex: Optimize atomic cmpxchg
  riscv: defconfig: enable pinctrl and dwmac support for TH1520

diff --combined Documentation/devicetree/bindings/riscv/cpus.yaml
index acb5b9ba6f0498e16d4dfadcec16b6c6f952b72c,c0cf6cf56749dcb281b61d297882cf810a016df7..2c72f148a74b019e46ad5917a0b75d45777c385e
--- 1/Documentation/devicetree/bindings/riscv/cpus.yaml
--- 2/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@@ -26,6 -26,18 +26,18 @@@ description: 
  allOf:
    - $ref: /schemas/cpu.yaml#
    - $ref: extensions.yaml
+   - if:
+       not:
+         properties:
+           compatible:
+             contains:
+               enum:
+                 - thead,c906
+                 - thead,c910
+                 - thead,c920
+     then:
+       properties:
+         thead,vlenb: false
  
  properties:
    compatible:
@@@ -46,7 -58,6 +58,7 @@@
                - sifive,u7
                - sifive,u74
                - sifive,u74-mc
 +              - spacemit,x60
                - thead,c906
                - thead,c908
                - thead,c910
@@@ -96,6 -107,13 +108,13 @@@
      description:
        The blocksize in bytes for the Zicboz cache operations.
  
+   thead,vlenb:
+     $ref: /schemas/types.yaml#/definitions/uint32
+     description:
+       VLEN/8, the vector register length in bytes. This property is required on
+       thead systems where the vector register length is not identical on all harts, or
+       the vlenb CSR is not available.
+ 
    # RISC-V has multiple properties for cache op block sizes as the sizes
    # differ between individual CBO extensions
    cache-op-block-size: false

diff --combined arch/riscv/configs/defconfig
index a924ef116d5e37f06a016f122214f6dec0a58bed,3049869a5ac07e4a55c7d959ecb0c84b9ce40f86..0f7dcbe3c45bb597158e4c3c074f312afb373630
--- 1/arch/riscv/configs/defconfig
--- 2/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@@ -10,7 -10,6 +10,6 @@@ CONFIG_MEMCG=
  CONFIG_BLK_CGROUP=y
  CONFIG_CGROUP_SCHED=y
  CONFIG_CFS_BANDWIDTH=y
- CONFIG_RT_GROUP_SCHED=y
  CONFIG_CGROUP_PIDS=y
  CONFIG_CGROUP_FREEZER=y
  CONFIG_CGROUP_HUGETLB=y
@@@ -30,7 -29,6 +29,7 @@@ CONFIG_ARCH_MICROCHIP=
  CONFIG_ARCH_RENESAS=y
  CONFIG_ARCH_SIFIVE=y
  CONFIG_ARCH_SOPHGO=y
 +CONFIG_ARCH_SPACEMIT=y
  CONFIG_SOC_STARFIVE=y
  CONFIG_ARCH_SUNXI=y
  CONFIG_ARCH_THEAD=y

diff --combined arch/riscv/kernel/process.c
index 7891294abf4937de3c7e440573844253e856b39f,6534264dfce260b3c05731bc587219c8d8f85408..7c244de7718008947075357ea4502d56419d507c
--- 1/arch/riscv/kernel/process.c
--- 2/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@@ -190,7 -190,7 +190,7 @@@ void flush_thread(void
  void arch_release_task_struct(struct task_struct *tsk)
  {
        /* Free the vector context of datap. */
-       if (has_vector())
+       if (has_vector() || has_xtheadvector())
                riscv_v_thread_free(tsk);
  }
  
@@@ -240,7 -240,7 +240,7 @@@ int copy_thread(struct task_struct *p, 
                p->thread.s[0] = 0;
        }
        p->thread.riscv_v_flags = 0;
-       if (has_vector())
+       if (has_vector() || has_xtheadvector())
                riscv_v_thread_alloc(p);
        p->thread.ra = (unsigned long)ret_from_fork;
        p->thread.sp = (unsigned long)childregs; /* kernel sp */
@@@ -364,7 -364,7 +364,7 @@@ static bool try_to_set_pmm(unsigned lon
   * disable it for tasks that already opted in to the relaxed ABI.
   */
  
 -static struct ctl_table tagged_addr_sysctl_table[] = {
 +static const struct ctl_table tagged_addr_sysctl_table[] = {
        {
                .procname       = "tagged_addr_disabled",
                .mode           = 0644,

diff --combined arch/riscv/kernel/vector.c
index d022b028ac3ff5375f522947d34166266ceb424a,aba5805119c33ae491fda6179902b3da16664de2..184f780c932d443d81eecac7a6fb8070ee7a5824
--- 1/arch/riscv/kernel/vector.c
--- 2/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@@ -33,7 -33,17 +33,17 @@@ int riscv_v_setup_vsize(void
  {
        unsigned long this_vsize;
  
-       /* There are 32 vector registers with vlenb length. */
+       /*
+        * There are 32 vector registers with vlenb length.
+        *
+        * If the thead,vlenb property was provided by the firmware, use that
+        * instead of probing the CSRs.
+        */
+       if (thead_vlenb_of) {
+               riscv_v_vsize = thead_vlenb_of * 32;
+               return 0;
+       }
+ 
        riscv_v_enable();
        this_vsize = csr_read(CSR_VLENB) * 32;
        riscv_v_disable();
@@@ -53,7 -63,7 +63,7 @@@
  
  void __init riscv_v_setup_ctx_cache(void)
  {
-       if (!has_vector())
+       if (!(has_vector() || has_xtheadvector()))
                return;
  
        riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx",
@@@ -173,7 -183,7 +183,7 @@@ bool riscv_v_first_use_handler(struct p
        u32 __user *epc = (u32 __user *)regs->epc;
        u32 insn = (u32)regs->badaddr;
  
-       if (!has_vector())
+       if (!(has_vector() || has_xtheadvector()))
                return false;
  
        /* Do not handle if V is not supported, or disabled */
@@@ -216,7 -226,7 +226,7 @@@ void riscv_v_vstate_ctrl_init(struct ta
        bool inherit;
        int cur, next;
  
-       if (!has_vector())
+       if (!(has_vector() || has_xtheadvector()))
                return;
  
        next = riscv_v_ctrl_get_next(tsk);
@@@ -238,7 -248,7 +248,7 @@@
  
  long riscv_v_vstate_ctrl_get_current(void)
  {
-       if (!has_vector())
+       if (!(has_vector() || has_xtheadvector()))
                return -EINVAL;
  
        return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK;
@@@ -249,7 -259,7 +259,7 @@@ long riscv_v_vstate_ctrl_set_current(un
        bool inherit;
        int cur, next;
  
-       if (!has_vector())
+       if (!(has_vector() || has_xtheadvector()))
                return -EINVAL;
  
        if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK)
@@@ -287,7 -297,7 +297,7 @@@
  
  #ifdef CONFIG_SYSCTL
  
 -static struct ctl_table riscv_v_default_vstate_table[] = {
 +static const struct ctl_table riscv_v_default_vstate_table[] = {
        {
                .procname       = "riscv_v_default_allow",
                .data           = &riscv_v_implicit_uacc,
@@@ -299,7 -309,7 +309,7 @@@
  
  static int __init riscv_v_sysctl_init(void)
  {
-       if (has_vector())
+       if (has_vector() || has_xtheadvector())
                if (!register_sysctl("abi", riscv_v_default_vstate_table))
                        return -EINVAL;
        return 0;
@@@ -309,7 -319,7 +319,7 @@@
  static int __init riscv_v_sysctl_init(void) { return 0; }
  #endif /* ! CONFIG_SYSCTL */
  
- static int riscv_v_init(void)
+ static int __init riscv_v_init(void)
  {
        return riscv_v_sysctl_init();
  }

diff --combined arch/riscv/mm/init.c
index 722178ae34883f742770ea5b9486b1ada3affb61,9641e4ad387f46cfdad7e88c4358f2f8f46a0396..15b2eda4c364b39261f94c371d791a24fb929aeb
--- 1/arch/riscv/mm/init.c
--- 2/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@@ -33,7 -33,6 +33,7 @@@
  #include <asm/pgtable.h>
  #include <asm/sections.h>
  #include <asm/soc.h>
 +#include <asm/sparsemem.h>
  #include <asm/tlbflush.h>
  
  #include "../kernel/head.h"
@@@ -63,13 -62,6 +63,13 @@@ EXPORT_SYMBOL(pgtable_l5_enabled)
  phys_addr_t phys_ram_base __ro_after_init;
  EXPORT_SYMBOL(phys_ram_base);
  
 +#ifdef CONFIG_SPARSEMEM_VMEMMAP
 +#define VMEMMAP_ADDR_ALIGN    (1ULL << SECTION_SIZE_BITS)
 +
 +unsigned long vmemmap_start_pfn __ro_after_init;
 +EXPORT_SYMBOL(vmemmap_start_pfn);
 +#endif
 +
  unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
                                                        __page_aligned_bss;
  EXPORT_SYMBOL(empty_zero_page);
@@@ -248,12 -240,8 +248,12 @@@ static void __init setup_bootmem(void
         * Make sure we align the start of the memory on a PMD boundary so that
         * at worst, we map the linear mapping with PMD mappings.
         */
 -      if (!IS_ENABLED(CONFIG_XIP_KERNEL))
 +      if (!IS_ENABLED(CONFIG_XIP_KERNEL)) {
                phys_ram_base = memblock_start_of_DRAM() & PMD_MASK;
 +#ifdef CONFIG_SPARSEMEM_VMEMMAP
 +              vmemmap_start_pfn = round_down(phys_ram_base, VMEMMAP_ADDR_ALIGN) >> PAGE_SHIFT;
 +#endif
 +      }
  
        /*
         * In 64-bit, any use of __va/__pa before this point is wrong as we
@@@ -268,8 -256,12 +268,12 @@@
         */
        if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) {
                max_mapped_addr = __pa(PAGE_OFFSET) + KERN_VIRT_SIZE;
-               memblock_cap_memory_range(phys_ram_base,
-                                         max_mapped_addr - phys_ram_base);
+               if (memblock_end_of_DRAM() > max_mapped_addr) {
+                       memblock_cap_memory_range(phys_ram_base,
+                                                 max_mapped_addr - phys_ram_base);
+                       pr_warn("Physical memory overflows the linear mapping size: region above %pa removed",
+                               &max_mapped_addr);
+               }
        }
  
        /*
@@@ -1113,9 -1105,6 +1117,9 @@@ asmlinkage void __init setup_vm(uintptr
        kernel_map.xiprom_sz = (uintptr_t)(&_exiprom) - (uintptr_t)(&_xiprom);
  
        phys_ram_base = CONFIG_PHYS_RAM_BASE;
 +#ifdef CONFIG_SPARSEMEM_VMEMMAP
 +      vmemmap_start_pfn = round_down(phys_ram_base, VMEMMAP_ADDR_ALIGN) >> PAGE_SHIFT;
 +#endif
        kernel_map.phys_addr = (uintptr_t)CONFIG_PHYS_RAM_BASE;
        kernel_map.size = (uintptr_t)(&_end) - (uintptr_t)(&_start);
  
@@@ -1573,7 -1562,7 +1577,7 @@@ static void __meminit free_pte_table(pt
                        return;
        }
  
 -      pagetable_pte_dtor(ptdesc);
 +      pagetable_dtor(ptdesc);
        if (PageReserved(page))
                free_reserved_page(page);
        else
@@@ -1581,7 -1570,7 +1585,7 @@@
        pmd_clear(pmd);
  }
  
 -static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud)
 +static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud, bool is_vmemmap)
  {
        struct page *page = pud_page(*pud);
        struct ptdesc *ptdesc = page_ptdesc(page);
@@@ -1594,8 -1583,7 +1598,8 @@@
                        return;
        }
  
 -      pagetable_pmd_dtor(ptdesc);
 +      if (!is_vmemmap)
 +              pagetable_dtor(ptdesc);
        if (PageReserved(page))
                free_reserved_page(page);
        else
@@@ -1719,7 -1707,7 +1723,7 @@@ static void __meminit remove_pud_mappin
                remove_pmd_mapping(pmd_base, addr, next, is_vmemmap, altmap);
  
                if (pgtable_l4_enabled)
 -                      free_pmd_table(pmd_base, pudp);
 +                      free_pmd_table(pmd_base, pudp, is_vmemmap);
        }
  }