]> Git Repo - linux.git/commitdiff
drm/amdgpu: update the handle ptr in soft_reset
authorSunil Khatri <[email protected]>
Mon, 30 Sep 2024 09:30:30 +0000 (15:00 +0530)
committerAlex Deucher <[email protected]>
Tue, 1 Oct 2024 21:45:44 +0000 (17:45 -0400)
Update the *handle to amdgpu_ip_block ptr for all
functions pointers of soft_reset.

Signed-off-by: Sunil Khatri <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
64 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/cik_ih.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/cz_ih.c
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
drivers/gpu/drm/amd/amdgpu/si.c
drivers/gpu/drm/amd/amdgpu/si_dma.c
drivers/gpu/drm/amd/amdgpu/si_ih.c
drivers/gpu/drm/amd/amdgpu/soc15.c
drivers/gpu/drm/amd/amdgpu/soc21.c
drivers/gpu/drm/amd/amdgpu/soc24.c
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
drivers/gpu/drm/amd/amdgpu/vi.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/include/amd_shared.h
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

index 8c85d7a9e0b0b8c43339f089312b8cda3900ec04..436f24d6bd830ac1fd6cb6c0e01772c3c8f3faec 100644 (file)
@@ -595,7 +595,7 @@ static int acp_wait_for_idle(void *handle)
        return 0;
 }
 
-static int acp_soft_reset(void *handle)
+static int acp_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index be5ec1d58b57c94652565556557aa88ab5ebb9cd..041eef115b215f371320d96c125c984c648f4faf 100644 (file)
@@ -5041,7 +5041,7 @@ static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
                        continue;
                if (adev->ip_blocks[i].status.hang &&
                    adev->ip_blocks[i].version->funcs->soft_reset) {
-                       r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
+                       r = adev->ip_blocks[i].version->funcs->soft_reset(&adev->ip_blocks[i]);
                        if (r)
                                return r;
                }
index f2198ac2796731a055037cb6d2f467e81f740ef0..e90b5f8074407d98168a780cdc1f710edc1beea2 100644 (file)
@@ -160,7 +160,7 @@ static int isp_wait_for_idle(void *handle)
        return 0;
 }
 
-static int isp_soft_reset(void *handle)
+static int isp_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index d2eafca7d32068a9e463f21421d18d781a43770b..af274e6b84224f2acccd36d20ae7719761d6a835 100644 (file)
@@ -637,7 +637,7 @@ static int amdgpu_vkms_wait_for_idle(void *handle)
        return 0;
 }
 
-static int amdgpu_vkms_soft_reset(void *handle)
+static int amdgpu_vkms_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 8e8e266b44ce693f2fde24e6ef0afeff96022140..b39944e3ac68537321f71c59a1f35895dba503f7 100644 (file)
@@ -2177,7 +2177,7 @@ static int cik_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int cik_common_soft_reset(void *handle)
+static int cik_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* XXX hard reset?? */
        return 0;
index 2ce7a6075a988b7a3e112a17916c5577b6f1e68d..612330f40447b8965349dfa7499d9c47f7080b02 100644 (file)
@@ -378,9 +378,9 @@ static int cik_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int cik_ih_soft_reset(void *handle)
+static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
index 6e7e78079630f9237349fffda8e0ec0ed538cdbc..8706855d681b7da2ad21e02f1785aec1346c1380 100644 (file)
@@ -54,7 +54,7 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
-static int cik_sdma_soft_reset(void *handle);
+static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block);
 
 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
@@ -1056,10 +1056,10 @@ static int cik_sdma_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int cik_sdma_soft_reset(void *handle)
+static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp;
 
        /* sdma0 */
index 71fe2131363555a3cc8268ee5cff70a7b93babf0..12a55f1e0e1f11b769fd5f5b10a81f03f721db44 100644 (file)
@@ -374,10 +374,10 @@ static int cz_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int cz_ih_soft_reset(void *handle)
+static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
        if (tmp & SRBM_STATUS__IH_BUSY_MASK)
index 4eb331336d9500137906858b5f7fc9bd8119e0d0..6f81621649d64bb7ead26f2e443cc29ce5e74b17 100644 (file)
@@ -2960,10 +2960,10 @@ static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
        return dce_v10_0_is_display_hung(adev);
 }
 
-static int dce_v10_0_soft_reset(void *handle)
+static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0, tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (dce_v10_0_is_display_hung(adev))
                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
index 9929b5bc6095933248fdfdeec55d66b641981dbc..b1afe4b837a760b7a358cb4cb8ebbbff0dc71f24 100644 (file)
@@ -3091,10 +3091,10 @@ static int dce_v11_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int dce_v11_0_soft_reset(void *handle)
+static int dce_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0, tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (dce_v11_0_is_display_hung(adev))
                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
index 7c464fc50dd6762dbfc7cfd2e7660f7da875f304..a6bbeb3bde3b353e644a8d10619a3aff9fdfed6f 100644 (file)
@@ -2848,7 +2848,7 @@ static int dce_v6_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int dce_v6_0_soft_reset(void *handle)
+static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
        return 0;
index 3fbc275a9c42111a3c98411c041ce1fad90f2a8b..0b57e22a7c95e21bba9d249a65aeb18d07f79a36 100644 (file)
@@ -2871,10 +2871,10 @@ static int dce_v8_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int dce_v8_0_soft_reset(void *handle)
+static int dce_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0, tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        if (dce_v8_0_is_display_hung(adev))
                srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
index 123da87a3142bcd0c79a4b6c6cb6bd3341886cad..c544ea2aea6e06eae95e6f5d37671b6a8c1d045a 100644 (file)
@@ -7495,11 +7495,11 @@ static int gfx_v10_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int gfx_v10_0_soft_reset(void *handle)
+static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 grbm_soft_reset = 0;
        u32 tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        /* GRBM_STATUS */
        tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
index df08f29843aeab10f23e40df6c1a1670e672be2f..ebf783763ac59900b2845cc2ee84586bfd8f4022 100644 (file)
@@ -4776,12 +4776,12 @@ int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev,
        return 0;
 }
 
-static int gfx_v11_0_soft_reset(void *handle)
+static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 grbm_soft_reset = 0;
        u32 tmp;
        int r, i, j, k;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
 
index 1fef47735da48cfd91025fd4b21cfaac9398187a..60579b3029b4046f556c734edc64c942798bb803 100644 (file)
@@ -3190,7 +3190,7 @@ static int gfx_v6_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int gfx_v6_0_soft_reset(void *handle)
+static int gfx_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 6fa6114e094d601ed9aa10d34dfb37db92c740a2..990e7de8da2589907428534cfd2352cb7847ea73 100644 (file)
@@ -4540,11 +4540,11 @@ static int gfx_v7_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int gfx_v7_0_soft_reset(void *handle)
+static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
        u32 tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        /* GRBM_STATUS */
        tmp = RREG32(mmGRBM_STATUS);
index 9a15bf5e6b93420fcc353297db16b29bcae019e4..0b72dc3062b59fe85bb48715c520483536ba89c2 100644 (file)
@@ -5024,9 +5024,9 @@ static int gfx_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-static int gfx_v8_0_soft_reset(void *handle)
+static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
        u32 tmp;
 
index 1deb5eee794fe770a0a4b55225e3f5ccf6a6622e..99334afb7aae7c635ecb294f4a3600ef49680353 100644 (file)
@@ -4108,11 +4108,11 @@ static int gfx_v9_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int gfx_v9_0_soft_reset(void *handle)
+static int gfx_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 grbm_soft_reset = 0;
        u32 tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        /* GRBM_STATUS */
        tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
index 27f331e2cdd963d8c1cc924ac24a172d35e59808..81bd4ca4fba5e80ee9e6bf9b7de3a330130a0b1b 100644 (file)
@@ -2423,11 +2423,11 @@ static int gfx_v9_4_3_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int gfx_v9_4_3_soft_reset(void *handle)
+static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 grbm_soft_reset = 0;
        u32 tmp;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        /* GRBM_STATUS */
        tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
index ff7596b5b306dd9eab47addfa39f9dfe5dc2fb3f..8e51c7e4e8c8efa7c6ba2fa392ece43f2697010c 100644 (file)
@@ -1088,7 +1088,7 @@ static int gmc_v10_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int gmc_v10_0_soft_reset(void *handle)
+static int gmc_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 3241effb67fa5a2dcfd65247afd6cb9d472d7cb6..2fc69cdf8843888a9e0933d2eb107c068c510708 100644 (file)
@@ -996,7 +996,7 @@ static int gmc_v11_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int gmc_v11_0_soft_reset(void *handle)
+static int gmc_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 745010a24a2f44798f3b696c3c2ab1a2ff14aa4f..3cbb5824a3785a52995a60191763e5521c0882e5 100644 (file)
@@ -980,7 +980,7 @@ static int gmc_v12_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int gmc_v12_0_soft_reset(void *handle)
+static int gmc_v12_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index e8566a53838ad7ecf38863c6f8849117d514d622..82a097d32f283d0d8ae0a28b12ede6dc853fdc66 100644 (file)
@@ -973,9 +973,9 @@ static int gmc_v6_0_wait_for_idle(void *handle)
 
 }
 
-static int gmc_v6_0_soft_reset(void *handle)
+static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
index 77e09503e2b96fb29f5507750617080c9a8b98f5..ad9bad951cc6fad43ec42fbe10babd8c2581da2e 100644 (file)
@@ -1167,9 +1167,9 @@ static int gmc_v7_0_wait_for_idle(void *handle)
 
 }
 
-static int gmc_v7_0_soft_reset(void *handle)
+static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
index f579c710d3d110f8698f3e62786a78c57c843a66..7ffb33dd54ef545dc52557cfd30857c73a31ecd0 100644 (file)
@@ -1330,9 +1330,9 @@ static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-static int gmc_v8_0_soft_reset(void *handle)
+static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->gmc.srbm_soft_reset)
index 24a269c2e4930b5859d9885e19f33e058350bc81..1d0eb31d7b72d0a68e7e20cf88bc109e994d4e77 100644 (file)
@@ -2461,7 +2461,7 @@ static int gmc_v9_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static int gmc_v9_0_soft_reset(void *handle)
+static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* XXX for emulation.*/
        return 0;
index 6e611aedf519c39fe54a6235ef7ccda2f44bec15..6210fa17eeca9b70b49858cb7b384b4e9eca47eb 100644 (file)
@@ -368,10 +368,10 @@ static int iceland_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int iceland_ih_soft_reset(void *handle)
+static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
        if (tmp & SRBM_STATUS__IH_BUSY_MASK)
index e2bf3b58fe07b4f0384ec0e5d2497fc601470881..80c021598b785d13686e12274ae66a266cfeaab8 100644 (file)
@@ -670,7 +670,7 @@ static int ih_v6_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int ih_v6_0_soft_reset(void *handle)
+static int ih_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
        return 0;
index a401324d8da0e915da715d1f8044e289da7b857c..be700137d5a72e282d2535511224b05eb3648e83 100644 (file)
@@ -649,7 +649,7 @@ static int ih_v6_1_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int ih_v6_1_soft_reset(void *handle)
+static int ih_v6_1_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
        return 0;
index 646e007ccc2ce9055ac2771118d4c22b1472bab3..a86d12e3ab2452a29db8cf6d0e11cbeddd1ea4ca 100644 (file)
@@ -639,7 +639,7 @@ static int ih_v7_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int ih_v7_0_soft_reset(void *handle)
+static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
        return 0;
index 93bf5e58cb49be62fb6836fd483e9d540002bcfa..85361dcb4b4ceb7b9189b8011a4af0b8aa4dbd9c 100644 (file)
@@ -644,7 +644,7 @@ static int navi10_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int navi10_ih_soft_reset(void *handle)
+static int navi10_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
        return 0;
index 8966a8b7c4ee023e4a44b60edf922dc1edcdc67a..7fdd5739b608e6e477d280718976ce7747b17a7b 100644 (file)
@@ -1053,7 +1053,7 @@ static int nv_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int nv_common_soft_reset(void *handle)
+static int nv_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 12add248325054d56203ac4bbc61bf43126a535c..a77977478ebef85e44547d9b37c487c1b921875e 100644 (file)
@@ -944,10 +944,10 @@ static int sdma_v2_4_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int sdma_v2_4_soft_reset(void *handle)
+static int sdma_v2_4_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp = RREG32(mmSRBM_STATUS2);
 
        if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
index e7f4f7138df0fc1a1ca33ce32cc9883d4236f6df..3e702853e0ac94639d0aab58100e6424d6f3756b 100644 (file)
@@ -1290,9 +1290,9 @@ static int sdma_v3_0_post_soft_reset(void *handle)
        return 0;
 }
 
-static int sdma_v3_0_soft_reset(void *handle)
+static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp;
 
index ae5abb9bfcb4415fe450d28c2b7533053f407a07..10887eeb50afed023dc1458736a94f8018db31b5 100644 (file)
@@ -2049,7 +2049,7 @@ static int sdma_v4_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int sdma_v4_0_soft_reset(void *handle)
+static int sdma_v4_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
 
index 5d5b8d5390851b2d31c62519bd96560c4b4d8c28..a8c5e30c83c8c7ec71f942b423f0dfc28dacc67e 100644 (file)
@@ -1559,7 +1559,7 @@ static int sdma_v4_4_2_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int sdma_v4_4_2_soft_reset(void *handle)
+static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
 
index ab230b3dfd9fc4afa335c0dcd53365b169daa5f0..c67ccb5411275f8ddc6da7ce4f134fd13e0ce4f7 100644 (file)
@@ -1548,7 +1548,7 @@ static int sdma_v5_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int sdma_v5_0_soft_reset(void *handle)
+static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
 
index ddbb26f4f4001d956384d8fc0dcf4f4ae47ad9d3..b136621e55490bc10cfe0cc8dea37f99137ff325 100644 (file)
@@ -761,9 +761,9 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
        return 0;
 }
 
-static int sdma_v5_2_soft_reset(void *handle)
+static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 grbm_soft_reset;
        u32 tmp;
        int i;
@@ -803,6 +803,7 @@ static int sdma_v5_2_soft_reset(void *handle)
 static int sdma_v5_2_start(struct amdgpu_device *adev)
 {
        int r = 0;
+       struct amdgpu_ip_block *ip_block;
 
        if (amdgpu_sriov_vf(adev)) {
                sdma_v5_2_ctx_switch_enable(adev, false);
@@ -823,7 +824,11 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
                        msleep(1000);
        }
 
-       sdma_v5_2_soft_reset(adev);
+       ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA);
+       if (!ip_block)
+               return -EINVAL;
+
+       sdma_v5_2_soft_reset(ip_block);
        /* unhalt the MEs */
        sdma_v5_2_enable(adev, true);
        /* enable sdma ring preemption */
index edf8f23a0211d8d211ec624ff0a91aafba3549fa..f18e3a40ceeb8431104054e453c75a1e0fe4894f 100644 (file)
@@ -755,9 +755,9 @@ static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
        return 0;
 }
 
-static int sdma_v6_0_soft_reset(void *handle)
+static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp;
        int i;
 
index 691870eca6d6fa5781a2c90d4fa531d7b389e2ef..670529e16289f2b01846ea0184df5996356e9f58 100644 (file)
@@ -747,9 +747,9 @@ static int sdma_v7_0_load_microcode(struct amdgpu_device *adev)
        return 0;
 }
 
-static int sdma_v7_0_soft_reset(void *handle)
+static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp;
        int i;
 
index b312c4cbcd982f1537d8a9dfea64423ec13f8d59..096cf2deeb4037140ddc60866d52a5808e4110c9 100644 (file)
@@ -2674,7 +2674,7 @@ static int si_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int si_common_soft_reset(void *handle)
+static int si_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 1e9669a7c7dd50ef44079e28f61f26a3eb48d4cb..93f80ab506265c4ad4bbb76a47f4033b96356fab 100644 (file)
@@ -571,7 +571,7 @@ static int si_dma_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int si_dma_soft_reset(void *handle)
+static int si_dma_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n");
        return 0;
index c8e664f27df1fd10c91d036d3094427a49f5e9e7..089921417ec5afa68dfe0b051c16b127603eb1cf 100644 (file)
@@ -240,9 +240,9 @@ static int si_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int si_ih_soft_reset(void *handle)
+static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(SRBM_STATUS);
index 62b7c1aa1f665cb8cafa0a6ea404ff5bce40e068..2f9f7e3fa8330bbab18e82d00f83a3ffde355faf 100644 (file)
@@ -1346,7 +1346,7 @@ static int soc15_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int soc15_common_soft_reset(void *handle)
+static int soc15_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 4ed3b821bf7914c06c2663dd8eedb150811c2712..5946911a419192480e69feed7cd52fa0575773ca 100644 (file)
@@ -939,7 +939,7 @@ static int soc21_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int soc21_common_soft_reset(void *handle)
+static int soc21_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 83714f409373d164ec2ec4f8152a930952e0c996..64d2f8ce548d75e9429c8da82ced2b21744a4b88 100644 (file)
@@ -536,7 +536,7 @@ static int soc24_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int soc24_common_soft_reset(void *handle)
+static int soc24_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 7cdf6a10607f21595088a18e63b50a817b1bd86a..59f167166f83f523391a6d40946bbce46593d0c8 100644 (file)
@@ -425,9 +425,9 @@ static int tonga_ih_post_soft_reset(void *handle)
        return tonga_ih_hw_init(adev);
 }
 
-static int tonga_ih_soft_reset(void *handle)
+static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->irq.srbm_soft_reset)
index c33b86f24a17c519dd67e0a647d79233d7eabdbe..0fd864247a48d02a8753980d968f4280a11a7967 100644 (file)
@@ -778,9 +778,9 @@ static int uvd_v3_1_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int uvd_v3_1_soft_reset(void *handle)
+static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        uvd_v3_1_stop(adev);
 
index de9e6222d495e853af8a0eb1087e5413f457f584..853af18fcc43d5701dc3ccad6b1e772f01687f80 100644 (file)
@@ -678,9 +678,9 @@ static int uvd_v4_2_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int uvd_v4_2_soft_reset(void *handle)
+static int uvd_v4_2_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        uvd_v4_2_stop(adev);
 
index f9bdbd1483833733947ff255183dfc9759d68649..7b6128660294fb85ecc98cb052100de0fc1c78b1 100644 (file)
@@ -600,9 +600,9 @@ static int uvd_v5_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int uvd_v5_0_soft_reset(void *handle)
+static int uvd_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        uvd_v5_0_stop(adev);
 
index 9e6043f578057bb16dca55320813b41444847d9b..1046ab677ea73afcd1c85c130d13a49f3c7dba13 100644 (file)
@@ -1195,9 +1195,9 @@ static int uvd_v6_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-static int uvd_v6_0_soft_reset(void *handle)
+static int uvd_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->uvd.inst->srbm_soft_reset)
index eebdf7b2d6336a2b465308caebff23b084a17c08..d4342556c09c2b957583603f58242268fe3264a5 100644 (file)
@@ -1517,9 +1517,9 @@ static int uvd_v7_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-static int uvd_v7_0_soft_reset(void *handle)
+static int uvd_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->uvd.inst[ring->me].srbm_soft_reset)
index cb77a9c12693c4b60fbf0312120397cfcc2e5034..71ca9966711ecde6f3e3edf887806fa52392c9b1 100644 (file)
@@ -532,9 +532,9 @@ static int vce_v2_0_resume(void *handle)
        return vce_v2_0_hw_init(adev);
 }
 
-static int vce_v2_0_soft_reset(void *handle)
+static int vce_v2_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
        mdelay(5);
index 6b7916c72193b515e3bd0f541ca7d299b725604d..34d7c2e4da8e9c10f0fe73a009567046987c7cca 100644 (file)
@@ -668,9 +668,9 @@ static bool vce_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
        }
 }
 
-static int vce_v3_0_soft_reset(void *handle)
+static int vce_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->vce.srbm_soft_reset)
index 83b7ce5e764fad5c9e2c283cae18666ec08327c7..b5399ecb6bb2c72361b054fc05e83731602409c9 100644 (file)
@@ -762,9 +762,9 @@ static bool vce_v4_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
        }
 }
 
-static int vce_v4_0_soft_reset(void *handle)
+static int vce_v4_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset;
 
        if (!adev->vce.srbm_soft_reset)
index 07c229d2c4e18530116ddaa71f52d749773ec4c9..2d80aafcdbc6756294a9cad103985c372f83d6ac 100644 (file)
@@ -576,7 +576,7 @@ static int vega10_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int vega10_ih_soft_reset(void *handle)
+static int vega10_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
 
index 89880d915fe41835f93e6e7eb7afa113e51fb12d..c2461211aefbf68c2d4c387957acefa297327ce9 100644 (file)
@@ -642,7 +642,7 @@ static int vega20_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static int vega20_ih_soft_reset(void *handle)
+static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* todo */
 
index a13f8edfd001a4bc4a4e01c5d473c0fea87336ed..e832dd50a62855cd618945bcb2f11756853b4f41 100644 (file)
@@ -1755,7 +1755,7 @@ static int vi_common_wait_for_idle(void *handle)
        return 0;
 }
 
-static int vi_common_soft_reset(void *handle)
+static int vi_common_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 51d692fffb67bcfbf4bddcae86acc068ff862cbe..d1ca9e709946060f06c7080065fc39ce2cb0809d 100644 (file)
@@ -331,7 +331,7 @@ static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)
        return false;
 }
 
-static int dm_soft_reset(void *handle)
+static int dm_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        /* XXX todo */
        return 0;
index 15cd8288b9acc4fe36f9514ae96c4f69b071c9d1..97a1726cd96859f61b6a26c0a3b7d93f98aec736 100644 (file)
@@ -394,7 +394,7 @@ struct amd_ip_funcs {
        int (*wait_for_idle)(void *handle);
        bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
        int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
-       int (*soft_reset)(void *handle);
+       int (*soft_reset)(struct amdgpu_ip_block *ip_block);
        int (*post_soft_reset)(void *handle);
        int (*set_clockgating_state)(void *handle,
                                     enum amd_clockgating_state state);
index 69aa62460a8d8f94f27cfb2403f25135ba7a71e6..92c7e45c64b2158d9340fcd03291ddc82a69cb65 100644 (file)
@@ -3105,7 +3105,7 @@ static int kv_dpm_wait_for_idle(void *handle)
 }
 
 
-static int kv_dpm_soft_reset(void *handle)
+static int kv_dpm_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 415c65148b46691b71d41755bc7a6e5bdd1d5946..157777db75c7be84543df556a879ea567a55e96f 100644 (file)
@@ -7849,7 +7849,7 @@ static int si_dpm_wait_for_idle(void *handle)
        return 0;
 }
 
-static int si_dpm_soft_reset(void *handle)
+static int si_dpm_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index 5c109be6bcbdc7ccda42b6079ccc77ede2be7976..334f03c042570ade744e7474b6565095a8fef1ef 100644 (file)
@@ -250,7 +250,7 @@ static int pp_wait_for_idle(void *handle)
        return 0;
 }
 
-static int pp_sw_reset(void *handle)
+static int pp_sw_reset(struct amdgpu_ip_block *ip_block)
 {
        return 0;
 }
index b32e4334c1743f4c35293e2b646458efc8a15899..2dd3867bb9b779393cd1a902c2def7e0628c5891 100644 (file)
@@ -2053,6 +2053,7 @@ static void smu_late_fini(struct amdgpu_ip_block *ip_block)
 static int smu_reset(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
+       struct amdgpu_ip_block *ip_block;
        int ret;
 
        ret = smu_hw_fini(adev);
@@ -2063,7 +2064,11 @@ static int smu_reset(struct smu_context *smu)
        if (ret)
                return ret;
 
-       ret = smu_late_init(&adev->ip_blocks[AMD_IP_BLOCK_TYPE_SMC]);
+       ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC);
+       if (!ip_block)
+               return -EINVAL;
+
+       ret = smu_late_init(ip_block);
        if (ret)
                return ret;
 
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