drm/amdgpu: Calling address translation functions to simplify codes

Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa
to simplify codes. No logic change.

Signed-off-by: Oak Zeng <[email protected]>
Signed-off-by: Harish Kasiviswanathan <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 4c5c19820d37fb68bd9e944841c88cc04c27de9f..4f10c452984068c08428f440ca9cc8675e23c798 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -205,7 +205,6 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
        struct drm_gem_object *gobj = NULL;
        struct amdgpu_bo *abo = NULL;
        int ret;
-       unsigned long tmp;
 
        memset(&mode_cmd, 0, sizeof(mode_cmd));
        mode_cmd.width = sizes->surface_width;
@@ -246,8 +245,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
 
        info->fbops = &amdgpufb_ops;
 
-       tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
-       info->fix.smem_start = adev->gmc.aper_base + tmp;
+       info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo);
        info->fix.smem_len = amdgpu_bo_size(abo);
        info->screen_base = amdgpu_bo_kptr(abo);
        info->screen_size = amdgpu_bo_size(abo);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 559582fac35e6f4dc702a7ee8370da18220d5701..1197f49eda185b2019ada23ceee1c01462c3e45b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -661,8 +661,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
        u64 vram_addr = adev->vm_manager.vram_base_offset -
                adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
        u64 vram_end = vram_addr + vram_size;
-       u64 gart_ptb_gpu_pa = amdgpu_bo_gpu_offset(adev->gart.bo) +
-               adev->vm_manager.vram_base_offset - adev->gmc.vram_start;
+       u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
 
        flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
        flags |= AMDGPU_PTE_WRITEABLE;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index d189507dcef0c43eb8b19080592bc9ab4287d7e7..7a278d8dc7096b492f03bae8960423b1e72653f0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -120,8 +120,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
                                max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-                       adev->vm_manager.vram_base_offset;
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 2aecc6a243e861317d71392584492c76ca8c113c..14c1c1a297dd3d75c3f585d65e0afa497087e849 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -165,8 +165,7 @@ static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
                             max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
-                       + adev->vm_manager.vram_base_offset;
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 410fd3a1a388eef2eea67cc8296ebcbd4b1655b6..41807817de7d9bf37236da93852a52eef3d50fd4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -164,8 +164,7 @@ static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
-               + adev->vm_manager.vram_base_offset;
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 2bfd620576f20637b25af7a8f54070c2fba20940..498b28a35f5b6bfcb4f9663469759340afeac670 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -568,8 +568,7 @@ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
                                 uint64_t *addr, uint64_t *flags)
 {
        if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
-               *addr = adev->vm_manager.vram_base_offset + *addr -
-                       adev->gmc.vram_start;
+               *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
        BUG_ON(*addr & 0xFFFF00000000003FULL);
 
        if (!adev->gmc.translate_further)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c82d82da2c7395cfb5b503925634574597ed1d17..f354f670c7add4b4e4034cc1fac8a96272bcc979 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1048,8 +1048,7 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
                                uint64_t *addr, uint64_t *flags)
 {
        if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
-               *addr = adev->vm_manager.vram_base_offset + *addr -
-                       adev->gmc.vram_start;
+               *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
        BUG_ON(*addr & 0xFFFF00000000003FULL);
 
        if (!adev->gmc.translate_further)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index aa9be5612c8908d62f6159605ee398c317c7289e..a99953833820ea4c48e21a163794ad0131de5a35 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -114,8 +114,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
                return;
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-               adev->vm_manager.vram_base_offset;
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index e3d3a9ab56e4176bddd023714fd3b9367a3d7317..f9dc13584f6c940d6b17653fa7d3953192d09332 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -135,8 +135,7 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
                return;
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-               adev->vm_manager.vram_base_offset;
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index da7edd1ed6b27c17cc1cef58421ef1ef43884b8d..ac76081b91d5caf6ed1109909e0b0f9552efd932 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -210,8 +210,7 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
        }
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-               adev->vm_manager.vram_base_offset;
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 1141c37432f065b07f7e47292e3a3581252fb6dd..a9899335d0b1fb0fea8e6168d85088c53e99d1d7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -162,8 +162,7 @@ static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-               adev->vm_manager.vram_base_offset;
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 0cffa820ea6e8ff49bc34f5c7a7b85c93023911a..1a92177c522f4783a044bb2f9a6aa75b8c880c6d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -136,8 +136,7 @@ static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
                        max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-                       adev->vm_manager.vram_base_offset;
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
                WREG32_SOC15_OFFSET(
                        MMHUB, 0,
                        mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,