Merge tag 'drm-next-2023-05-05' of git://anongit.freedesktop.org/drm/drm

Pull more drm fixes from Dave Airlie:
 "This is the fixes for the last couple of weeks for i915 and last 3
  weeks for amdgpu, lots of them but pretty scattered around and all
  pretty small.

  amdgpu:
   - SR-IOV fixes
   - DCN 3.2 fixes
   - DC mclk handling fixes
   - eDP fixes
   - SubVP fixes
   - HDCP regression fix
   - DSC fixes
   - DC FP fixes
   - DCN 3.x fixes
   - Display flickering fix when switching between vram and gtt
   - Z8 power saving fix
   - Fix hang when skipping modeset
   - GPU reset fixes
   - Doorbell fix when resizing BARs
   - Fix spurious warnings in gmc
   - Locking fix for AMDGPU_SCHED IOCTL
   - SR-IOV fix
   - DCN 3.1.4 fix
   - DCN 3.2 fix
   - Fix job cleanup when CS is aborted

  i915:
   - skl pipe source size check
   - mtl transcoder mask fix
   - DSI power on sequence fix
   - GuC versioning corner case fix"

* tag 'drm-next-2023-05-05' of git://anongit.freedesktop.org/drm/drm: (48 commits)
  drm/amdgpu: drop redundant sched job cleanup when cs is aborted
  drm/amd/display: filter out invalid bits in pipe_fuses
  drm/amd/display: Change default Z8 watermark values
  drm/amdgpu: disable SDMA WPTR_POLL_ENABLE for SR-IOV
  drm/amdgpu: add a missing lock for AMDGPU_SCHED
  drm/amdgpu: fix an amdgpu_irq_put() issue in gmc_v9_0_hw_fini()
  drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini
  drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini
  drm/amdgpu: Enable doorbell selfring after resize FB BAR
  drm/amdgpu: Use the default reset when loading or reloading the driver
  drm/amdgpu: Fix mode2 reset for sienna cichlid
  drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
  drm/i915/mtl: Add the missing CPU transcoder mask in intel_device_info
  drm/i915/guc: Actually return an error if GuC version range check fails
  drm/amd/display: Lowering min Z8 residency time
  drm/amd/display: fix flickering caused by S/G mode
  drm/amd/display: Set min_width and min_height capability for DCN30
  drm/amd/display: Isolate remaining FPU code in DCN32
  drm/amd/display: Update bounding box values for DCN321
  drm/amd/display: Do not clear GPINT register when releasing DMUB from reset
  ...

diff --combined drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c4aa87086a4e79689501ae470732908ef9998be4,8d17fd5a817e0a62a7a33b4b59af1c6ee6ef2c9c..8b4b186c57f515fd541eaa15ce55e0b3ebf2dadb
--- 1/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
--- 2/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@@ -3128,9 -3128,12 +3128,12 @@@ void amdgpu_dm_update_connector_after_d
                                                    aconnector->edid);
                }
  
-               aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
-               if (!aconnector->timing_requested)
-                       dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
+               if (!aconnector->timing_requested) {
+                       aconnector->timing_requested =
+                               kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
+                       if (!aconnector->timing_requested)
+                               dm_error("failed to create aconnector->requested_timing\n");
+               }
  
                drm_connector_update_edid_property(connector, aconnector->edid);
                amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
@@@ -4471,6 -4474,10 +4474,6 @@@ static int amdgpu_dm_initialize_drm_dev
                amdgpu_set_panel_orientation(&aconnector->base);
        }
  
 -      /* If we didn't find a panel, notify the acpi video detection */
 -      if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
 -              acpi_video_report_nolcd();
 -
        /* Software is initialized. Now we can register interrupt handlers. */
        switch (adev->asic_type) {
  #if defined(CONFIG_DRM_AMD_DC_SI)
@@@ -7894,6 -7901,13 +7897,13 @@@ static void amdgpu_dm_commit_cursors(st
                        amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
  }
  
+ static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
+ {
+       struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
+ 
+       return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
+ }
+ 
  static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                    struct dc_state *dc_state,
                                    struct drm_device *dev,
@@@ -7968,6 -7982,8 +7978,8 @@@
                        continue;
  
                dc_plane = dm_new_plane_state->dc_state;
+               if (!dc_plane)
+                       continue;
  
                bundle->surface_updates[planes_count].surface = dc_plane;
                if (new_pcrtc_state->color_mgmt_changed) {
@@@ -8034,11 -8050,13 +8046,13 @@@
  
                /*
                 * Only allow immediate flips for fast updates that don't
-                * change FB pitch, DCC state, rotation or mirroing.
+                * change memory domain, FB pitch, DCC state, rotation or
+                * mirroring.
                 */
                bundle->flip_addrs[planes_count].flip_immediate =
                        crtc->state->async_flip &&
-                       acrtc_state->update_type == UPDATE_TYPE_FAST;
+                       acrtc_state->update_type == UPDATE_TYPE_FAST &&
+                       get_mem_type(old_plane_state->fb) == get_mem_type(fb);
  
                timestamp_ns = ktime_get_ns();
                bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
@@@ -8550,6 -8568,9 +8564,9 @@@ static void amdgpu_dm_atomic_commit_tai
                struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
                struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  
+               if (!adev->dm.hdcp_workqueue)
+                       continue;
+ 
                pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
  
                if (!connector)
@@@ -8598,6 -8619,9 +8615,9 @@@
                struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
                struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
  
+               if (!adev->dm.hdcp_workqueue)
+                       continue;
+ 
                new_crtc_state = NULL;
                old_crtc_state = NULL;
  
@@@ -9616,8 -9640,9 +9636,9 @@@ static int dm_update_plane_state(struc
                        return -EINVAL;
                }
  
+               if (dm_old_plane_state->dc_state)
+                       dc_plane_state_release(dm_old_plane_state->dc_state);
  
-               dc_plane_state_release(dm_old_plane_state->dc_state);
                dm_new_plane_state->dc_state = NULL;
  
                *lock_and_validation_needed = true;
@@@ -10154,6 -10179,7 +10175,7 @@@ static int amdgpu_dm_atomic_check(struc
                ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
                if (ret) {
                        DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
+                       ret = -EINVAL;
                        goto fail;
                }
  

diff --combined drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 24806acc84385ad9ebb055326bf959ed63af6762,2f7df8d34a91e8f6771467901814850e05248542..abeeede38fb3912f904a864ec08320e7cadba93e
--- 1/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
--- 2/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@@ -885,7 -885,7 +885,7 @@@ static const struct dc_plane_cap plane_
  static const struct dc_debug_options debug_defaults_drv = {
        .disable_z10 = false,
        .enable_z9_disable_interface = true,
-       .minimum_z8_residency_time = 3080,
+       .minimum_z8_residency_time = 2000,
        .psr_skip_crtc_disable = true,
        .disable_dmcu = true,
        .force_abm_enable = false,
@@@ -1696,23 -1696,6 +1696,23 @@@ static void dcn314_get_panel_config_def
        *panel_config = panel_config_defaults;
  }
  
 +static bool filter_modes_for_single_channel_workaround(struct dc *dc,
 +              struct dc_state *context)
 +{
 +      // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
 +      if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
 +              int total_phy_pix_clk = 0;
 +
 +              for (int i = 0; i < context->stream_count; i++)
 +                      if (context->res_ctx.pipe_ctx[i].stream)
 +                              total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
 +
 +              if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
 +                      return true;
 +      }
 +      return false;
 +}
 +
  bool dcn314_validate_bandwidth(struct dc *dc,
                struct dc_state *context,
                bool fast_validate)
@@@ -1728,9 -1711,6 +1728,9 @@@
  
        BW_VAL_TRACE_COUNT();
  
 +      if (filter_modes_for_single_channel_workaround(dc, context))
 +              goto validate_fail;
 +
        DC_FP_START();
        // do not support self refresh only
        out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);