ARM: mm: improve do_ldrd_abort macro

Improve the do_ldrd_abort macro code - firstly, it inefficiently checks
for the LDRD encoding by doing a multi-stage test of various bits.  This
can be simplified by generating a mask, bitmasking the instruction and
then comparing the result.

Secondly, we want to be able to test the result rather than branching
to do_DataAbort, so remove the branch at the end and rename the macro
to 'teq_ldrd' to reflect it's new usage.  teq_ldrd macro returns 'eq'
if the instruction was a LDRD.

Signed-off-by: Russell King <[email protected]>

diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index a0908d4653a34a2241d95c58af16dcdde4dafa9a..c913031b79ccba32d12b75d684210c44c5247133 100644 (file)
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -22,7 +22,8 @@ ENTRY(v5t_early_abort)
        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
        ldreq   r3, [r4]                        @ read aborted ARM instruction
        bic     r1, r1, #1 << 11                @ clear bits 11 of FSR
-       do_ldrd_abort tmp=ip, insn=r3
+       teq_ldrd tmp=ip, insn=r3                @ insn was LDRD?
+       beq     do_DataAbort                    @ yes
        tst     r3, #1 << 20                    @ check write
        orreq   r1, r1, #1 << 11
        b       do_DataAbort

diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index 4006b7a612642b7fa4ec36b5a995ccc9bc1e3a40..1b80d71adb0ff15283a44c5f51d0480487298196 100644 (file)
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -24,7 +24,8 @@ ENTRY(v5tj_early_abort)
        bne     do_DataAbort
        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
        ldreq   r3, [r4]                        @ read aborted ARM instruction
-       do_ldrd_abort tmp=ip, insn=r3
+       teq_ldrd tmp=ip, insn=r3                @ insn was LDRD?
+       beq     do_DataAbort                    @ yes
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
        b       do_DataAbort

diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 8c48c5c22a331aac8f547335d6990c598457ef0b..113704f30e9f8825b624b9c01f115464c4b9998a 100644 (file)
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -34,7 +34,8 @@ ENTRY(v6_early_abort)
        ldr     r3, [r4]                        @ read aborted ARM instruction
  ARM_BE8(rev   r3, r3)
 
-       do_ldrd_abort tmp=ip, insn=r3
+       teq_ldrd tmp=ip, insn=r3                @ insn was LDRD?
+       beq     do_DataAbort                    @ yes
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
 #endif

diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index 2cbf68ef0e8321121e5ecabb55f50f95083beb1d..50d6c0a900b14d900d40d64a0961ddf15f752e14 100644 (file)
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -29,12 +29,9 @@ not_thumb:
  *   [7:4] == 1101
  *    [20] == 0
  */
-       .macro  do_ldrd_abort, tmp, insn
-       tst     \insn, #0x0e100000              @ [27:25,20] == 0
-       bne     not_ldrd
-       and     \tmp, \insn, #0x000000f0        @ [7:4] == 1101
-       cmp     \tmp, #0x000000d0
-       beq     do_DataAbort
-not_ldrd:
+       .macro  teq_ldrd, tmp, insn
+       mov     \tmp, #0x0e100000
+       orr     \tmp, #0x000000f0
+       and     \tmp, \insn, \tmp
+       teq     \tmp, #0x000000d0
        .endm
-