x86/mce/amd: Add PPIN support for AMD MCE

Newer AMD CPUs support a feature called protected processor
identification number (PPIN). This feature can be detected via
CPUID_Fn80000008_EBX[23].

However, CPUID alone is not enough to read the processor identification
number - MSR_AMD_PPIN_CTL also needs to be configured properly. If, for
any reason, MSR_AMD_PPIN_CTL[PPIN_EN] can not be turned on, such as
disabled in BIOS, the CPU capability bit X86_FEATURE_AMD_PPIN needs to
be cleared.

When the X86_FEATURE_AMD_PPIN capability is available, the
identification number is issued together with the MCE error info in
order to keep track of the source of MCE errors.

 [ bp: Massage. ]

Co-developed-by: Smita Koralahalli Channabasappa <[email protected]>
Signed-off-by: Smita Koralahalli Channabasappa <[email protected]>
Signed-off-by: Wei Huang <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Acked-by: Tony Luck <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f3327cb56edfe163d1a8fc0a45b89fb324573243..4b263ffb793be39047939df398a7e07e51393ecd 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,6 +299,7 @@
 #define X86_FEATURE_AMD_IBRS           (13*32+14) /* "" Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP          (13*32+15) /* "" Single Thread Indirect Branch Predictors */
 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON        (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
+#define X86_FEATURE_AMD_PPIN           (13*32+23) /* Protected Processor Inventory Number */
 #define X86_FEATURE_AMD_SSBD           (13*32+24) /* "" Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD          (13*32+25) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_AMD_SSB_NO         (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ac83a0fef6285d9901bf44b2b5169ab9fef89698..a2cd870af7f588880aa1e1902ddca75cbc890871 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -393,6 +393,35 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
        per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 }
 
+static void amd_detect_ppin(struct cpuinfo_x86 *c)
+{
+       unsigned long long val;
+
+       if (!cpu_has(c, X86_FEATURE_AMD_PPIN))
+               return;
+
+       /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */
+       if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val))
+               goto clear_ppin;
+
+       /* PPIN is locked in disabled mode, clear feature bit */
+       if ((val & 3UL) == 1UL)
+               goto clear_ppin;
+
+       /* If PPIN is disabled, try to enable it */
+       if (!(val & 2UL)) {
+               wrmsrl_safe(MSR_AMD_PPIN_CTL,  val | 2UL);
+               rdmsrl_safe(MSR_AMD_PPIN_CTL, &val);
+       }
+
+       /* If PPIN_EN bit is 1, return from here; otherwise fall through */
+       if (val & 2UL)
+               return;
+
+clear_ppin:
+       clear_cpu_cap(c, X86_FEATURE_AMD_PPIN);
+}
+
 u16 amd_get_nb_id(int cpu)
 {
        return per_cpu(cpu_llc_id, cpu);
@@ -940,6 +969,7 @@ static void init_amd(struct cpuinfo_x86 *c)
        amd_detect_cmp(c);
        amd_get_topology(c);
        srat_detect_node(c);
+       amd_detect_ppin(c);
 
        init_amd_cacheinfo(c);
 

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index fe3983d551cc16c48c8f42504e4ffc930e8ec00b..dd06fce537fccbc193f7022f25bfa80c52a97846 100644 (file)
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -142,6 +142,8 @@ void mce_setup(struct mce *m)
 
        if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
                rdmsrl(MSR_PPIN, m->ppin);
+       else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
+               rdmsrl(MSR_AMD_PPIN, m->ppin);
 
        m->microcode = boot_cpu_data.microcode;
 }