octeontx2-pf: Fix coverity and klockwork issues in octeon PF driver

Fix unintended sign extension and klockwork issues. These are not real
issue but for sanity checks.

Signed-off-by: Ratheesh Kannoth <[email protected]>
Signed-off-by: Suman Ghosh <[email protected]>
Signed-off-by: David S. Miller <[email protected]>

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
index a85ac039d779be0681b7339c291cf02a616d1d37..87d5776e3b88e922c6196df50dc2bd65f85a0e0f 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c
@@ -648,14 +648,14 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for
        } else if (lvl == NIX_TXSCH_LVL_TL4) {
                parent = schq_list[NIX_TXSCH_LVL_TL3][prio];
                req->reg[0] = NIX_AF_TL4X_PARENT(schq);
-               req->regval[0] = parent << 16;
+               req->regval[0] = (u64)parent << 16;
                req->num_regs++;
                req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
                req->regval[1] = dwrr_val;
        } else if (lvl == NIX_TXSCH_LVL_TL3) {
                parent = schq_list[NIX_TXSCH_LVL_TL2][prio];
                req->reg[0] = NIX_AF_TL3X_PARENT(schq);
-               req->regval[0] = parent << 16;
+               req->regval[0] = (u64)parent << 16;
                req->num_regs++;
                req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
                req->regval[1] = dwrr_val;
@@ -670,11 +670,11 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for
        } else if (lvl == NIX_TXSCH_LVL_TL2) {
                parent = schq_list[NIX_TXSCH_LVL_TL1][prio];
                req->reg[0] = NIX_AF_TL2X_PARENT(schq);
-               req->regval[0] = parent << 16;
+               req->regval[0] = (u64)parent << 16;
 
                req->num_regs++;
                req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
-               req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
+               req->regval[1] = (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val;
 
                if (lvl == hw->txschq_link_cfg_lvl) {
                        req->num_regs++;
@@ -698,7 +698,7 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for
 
                req->num_regs++;
                req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
-               req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
+               req->regval[1] = hw->txschq_aggr_lvl_rr_prio << 1;
 
                req->num_regs++;
                req->reg[2] = NIX_AF_TL1X_CIR(schq);

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h
index 45a32e4b49d1cb458e41e8628aea68b0b990a610..e3aee6e3621517e7f64cd1fcbe6ce609cc0a47b0 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h
@@ -139,33 +139,34 @@
 #define        NIX_LF_CINTX_ENA_W1C(a)         (NIX_LFBASE | 0xD50 | (a) << 12)
 
 /* NIX AF transmit scheduler registers */
-#define NIX_AF_SMQX_CFG(a)             (0x700 | (a) << 16)
-#define NIX_AF_TL1X_SCHEDULE(a)                (0xC00 | (a) << 16)
-#define NIX_AF_TL1X_CIR(a)             (0xC20 | (a) << 16)
-#define NIX_AF_TL1X_TOPOLOGY(a)                (0xC80 | (a) << 16)
-#define NIX_AF_TL2X_PARENT(a)          (0xE88 | (a) << 16)
-#define NIX_AF_TL2X_SCHEDULE(a)                (0xE00 | (a) << 16)
-#define NIX_AF_TL2X_TOPOLOGY(a)                (0xE80 | (a) << 16)
-#define NIX_AF_TL2X_CIR(a)              (0xE20 | (a) << 16)
-#define NIX_AF_TL2X_PIR(a)              (0xE30 | (a) << 16)
-#define NIX_AF_TL3X_PARENT(a)          (0x1088 | (a) << 16)
-#define NIX_AF_TL3X_SCHEDULE(a)                (0x1000 | (a) << 16)
-#define NIX_AF_TL3X_SHAPE(a)           (0x1010 | (a) << 16)
-#define NIX_AF_TL3X_CIR(a)             (0x1020 | (a) << 16)
-#define NIX_AF_TL3X_PIR(a)             (0x1030 | (a) << 16)
-#define NIX_AF_TL3X_TOPOLOGY(a)                (0x1080 | (a) << 16)
-#define NIX_AF_TL4X_PARENT(a)          (0x1288 | (a) << 16)
-#define NIX_AF_TL4X_SCHEDULE(a)                (0x1200 | (a) << 16)
-#define NIX_AF_TL4X_SHAPE(a)           (0x1210 | (a) << 16)
-#define NIX_AF_TL4X_CIR(a)             (0x1220 | (a) << 16)
-#define NIX_AF_TL4X_PIR(a)             (0x1230 | (a) << 16)
-#define NIX_AF_TL4X_TOPOLOGY(a)                (0x1280 | (a) << 16)
-#define NIX_AF_MDQX_SCHEDULE(a)                (0x1400 | (a) << 16)
-#define NIX_AF_MDQX_SHAPE(a)           (0x1410 | (a) << 16)
-#define NIX_AF_MDQX_CIR(a)             (0x1420 | (a) << 16)
-#define NIX_AF_MDQX_PIR(a)             (0x1430 | (a) << 16)
-#define NIX_AF_MDQX_PARENT(a)          (0x1480 | (a) << 16)
-#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b)        (0x1700 | (a) << 16 | (b) << 3)
+#define NIX_AF_SMQX_CFG(a)             (0x700 | (u64)(a) << 16)
+#define NIX_AF_TL4X_SDP_LINK_CFG(a)    (0xB10 | (u64)(a) << 16)
+#define NIX_AF_TL1X_SCHEDULE(a)                (0xC00 | (u64)(a) << 16)
+#define NIX_AF_TL1X_CIR(a)             (0xC20 | (u64)(a) << 16)
+#define NIX_AF_TL1X_TOPOLOGY(a)                (0xC80 | (u64)(a) << 16)
+#define NIX_AF_TL2X_PARENT(a)          (0xE88 | (u64)(a) << 16)
+#define NIX_AF_TL2X_SCHEDULE(a)                (0xE00 | (u64)(a) << 16)
+#define NIX_AF_TL2X_TOPOLOGY(a)                (0xE80 | (u64)(a) << 16)
+#define NIX_AF_TL2X_CIR(a)             (0xE20 | (u64)(a) << 16)
+#define NIX_AF_TL2X_PIR(a)             (0xE30 | (u64)(a) << 16)
+#define NIX_AF_TL3X_PARENT(a)          (0x1088 | (u64)(a) << 16)
+#define NIX_AF_TL3X_SCHEDULE(a)                (0x1000 | (u64)(a) << 16)
+#define NIX_AF_TL3X_SHAPE(a)           (0x1010 | (u64)(a) << 16)
+#define NIX_AF_TL3X_CIR(a)             (0x1020 | (u64)(a) << 16)
+#define NIX_AF_TL3X_PIR(a)             (0x1030 | (u64)(a) << 16)
+#define NIX_AF_TL3X_TOPOLOGY(a)                (0x1080 | (u64)(a) << 16)
+#define NIX_AF_TL4X_PARENT(a)          (0x1288 | (u64)(a) << 16)
+#define NIX_AF_TL4X_SCHEDULE(a)                (0x1200 | (u64)(a) << 16)
+#define NIX_AF_TL4X_SHAPE(a)           (0x1210 | (u64)(a) << 16)
+#define NIX_AF_TL4X_CIR(a)             (0x1220 | (u64)(a) << 16)
+#define NIX_AF_TL4X_PIR(a)             (0x1230 | (u64)(a) << 16)
+#define NIX_AF_TL4X_TOPOLOGY(a)                (0x1280 | (u64)(a) << 16)
+#define NIX_AF_MDQX_SCHEDULE(a)                (0x1400 | (u64)(a) << 16)
+#define NIX_AF_MDQX_SHAPE(a)           (0x1410 | (u64)(a) << 16)
+#define NIX_AF_MDQX_CIR(a)             (0x1420 | (u64)(a) << 16)
+#define NIX_AF_MDQX_PIR(a)             (0x1430 | (u64)(a) << 16)
+#define NIX_AF_MDQX_PARENT(a)          (0x1480 | (u64)(a) << 16)
+#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b)        (0x1700 | (u64)(a) << 16 | (b) << 3)
 
 /* LMT LF registers */
 #define LMT_LFBASE                     BIT_ULL(RVU_FUNC_BLKADDR_SHIFT)

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
index 929b4eac25d974a0263281c8bcc76b53c137a05d..3eb85949677ad2bf512d68a301633204c49e2f17 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
@@ -513,7 +513,7 @@ process_cqe:
 
 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll)
 {
-       struct dim_sample dim_sample;
+       struct dim_sample dim_sample = { 0 };
        u64 rx_frames, rx_bytes;
        u64 tx_frames, tx_bytes;
 

diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/qos.c b/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
index edac008099c0c41def858e1bca01d7d22e8ffe10..0f844c14485a0e35fe15ac3dd3b9100830bad146 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
+++ b/drivers/net/ethernet/marvell/octeontx2/nic/qos.c
@@ -153,7 +153,6 @@ static void __otx2_qos_txschq_cfg(struct otx2_nic *pfvf,
                num_regs++;
 
                otx2_config_sched_shaping(pfvf, node, cfg, &num_regs);
-
        } else if (level == NIX_TXSCH_LVL_TL4) {
                otx2_config_sched_shaping(pfvf, node, cfg, &num_regs);
        } else if (level == NIX_TXSCH_LVL_TL3) {
@@ -176,7 +175,7 @@ static void __otx2_qos_txschq_cfg(struct otx2_nic *pfvf,
                /* check if node is root */
                if (node->qid == OTX2_QOS_QID_INNER && !node->parent) {
                        cfg->reg[num_regs] = NIX_AF_TL2X_SCHEDULE(node->schq);
-                       cfg->regval[num_regs] =  TXSCH_TL1_DFLT_RR_PRIO << 24 |
+                       cfg->regval[num_regs] =  (u64)hw->txschq_aggr_lvl_rr_prio << 24 |
                                                 mtu_to_dwrr_weight(pfvf,
                                                                    pfvf->tx_max_pktlen);
                        num_regs++;