Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver updates from Stephen Boyd:
 "A pile of clk driver updates with a small tracepoint patch to the clk
  core this time around.

  The core framework is effectively unchanged, with the majority of the
  diff going to the Qualcomm clk driver directory because they added two
  3k line files that are almost all clk data (Abel Vesa from Linaro
  tried to shrink the number of lines down, but it doesn't seem to be
  possible without sacrificing readability).

  The second big driver this time around is the Rockchip rk3588 clk and
  reset unit, at _only_ 2.5k lines.

  Ignoring the big clk drivers from the familiar SoC vendors, there's
  just a bunch of little clk driver updates and fixes throughout here.

  It's the usual set of clk data fixups to describe proper parents, or
  add frequencies to frequency tables, or plug memory leaks when
  function calls fail. Also, some drivers are converted to use modern
  clk_hw APIs, which is always nice to see. And data is deduplicated,
  leading to a smaller kernel Image.

  Overall this batch has a larger collection of cleanups than it
  typically does. Maybe that means there are less new SoCs right now
  that need supporting, and the focus has shifted to quality and
  reliability. I can dream.

  New Drivers:
   - Frequency hopping controller hardware on MediaTek MT8186
   - Global clock controller for Qualcomm SM8550
   - Display clock controller for Qualcomm SC8280XP
   - RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
   - CPU PLL on MStar/SigmaStar SoCs
   - Support for the clock and reset unit of the Rockchip rk3588

  Updates:
   - Tracepoints for clk_rate_request structures
   - Debugfs support for fractional divider clk
   - Make MxL's CGU driver secure compatible
   - Ingenic JZ4755 SoC clk support
   - Support audio clks on X1000 SoCs
   - Remove flags from univ/main/syspll child fixed factor clocks across
     MediaTek platforms
   - Fix clock dependency for ADC on MediaTek MT7986
   - Fix parent for FlexSPI clock for i.MX93
   - Add USB suspend clock on i.MX8MP
   - Unmap anatop base on error for i.MX93 driver
   - Change enet clock parent to wakeup_axi_root for i.MX93
   - Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
   - Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
   - Add 320MHz and 640MHz entries to PLL146x
   - Add audio shared gate and SAI clocks for i.MX8MP
   - Fix a possible memory leak in the error path of rockchip PLL
     creation
   - Fix header guard for V3S clocks
   - Add IR module clock for f1c100s
   - Correct the parent clocks for the (High Speed) Serial Communication
     Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
     Switch clocks on Renesas R-Car S4-8
   - Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
     R-Car V4H
   - Two PLL driver fixups for the Amlogic clk driver
   - Round SD clock rate to improve parent clock selection
   - Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
     S4-8
   - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
     serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI
     (RPC-IF) clocks on Renesas R-Car V4H
   - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
     Renesas RZ/G2L
   - Fix endless loop on Renesas RZ/N1
   - Correct the parent clocks for the High Speed Serial Communication
     Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
     Note: HSCIF0 is used for the serial console on the White-Hawk
     development board
   - Various clk DT binding improvements and conversions to YAML
   - Qualcomm SM8150/SM8250 display clock controller cleaned up
   - Some missing clocks for Qualcomm SM8350 added
   - Qualcomm MSM8974 Global and Multimedia clock controllers
     transitioned to parent_data and parent_hws
   - Use parent_data and add network resets for Qualcomm IPQ8074
   - Qualcomm Krait clock controller modernized
   - Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
     controllers
   - Enable retention mode on Qualcomm SM8250 USB GDSCs
   - Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
     clocks which definition could be shared between platforms
   - Various NULL pointer checks added for allocations"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (188 commits)
  clk: nomadik: correct struct name kernel-doc warning
  clk: lmk04832: fix kernel-doc warnings
  clk: lmk04832: drop superfluous #include
  clk: lmk04832: drop unnecessary semicolons
  clk: lmk04832: declare variables as const when possible
  clk: socfpga: Fix memory leak in socfpga_gate_init()
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: st: Fix memory leak in st_of_quadfs_setup()
  clk: samsung: Fix memory leak in _samsung_clk_register_pll()
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  ...

diff --combined drivers/clk/socfpga/clk-gate.c
index 3e347b9e9eff8c84cad6c764cf9dbf844cba1199,c94b59b80dd43c29c76ce8c02b48e878a5c37f06..0c18c55edf8cebc40751b65c68536c309e2a7f93
--- 1/drivers/clk/socfpga/clk-gate.c
--- 2/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@@ -108,7 -108,61 +108,7 @@@ static unsigned long socfpga_clk_recalc
        return parent_rate / div;
  }
  
 -static int socfpga_clk_prepare(struct clk_hw *hwclk)
 -{
 -      struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
 -      struct regmap *sys_mgr_base_addr;
 -      int i;
 -      u32 hs_timing;
 -      u32 clk_phase[2];
 -
 -      if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
 -              sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
 -              if (IS_ERR(sys_mgr_base_addr)) {
 -                      pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
 -                      return -EINVAL;
 -              }
 -
 -              for (i = 0; i < 2; i++) {
 -                      switch (socfpgaclk->clk_phase[i]) {
 -                      case 0:
 -                              clk_phase[i] = 0;
 -                              break;
 -                      case 45:
 -                              clk_phase[i] = 1;
 -                              break;
 -                      case 90:
 -                              clk_phase[i] = 2;
 -                              break;
 -                      case 135:
 -                              clk_phase[i] = 3;
 -                              break;
 -                      case 180:
 -                              clk_phase[i] = 4;
 -                              break;
 -                      case 225:
 -                              clk_phase[i] = 5;
 -                              break;
 -                      case 270:
 -                              clk_phase[i] = 6;
 -                              break;
 -                      case 315:
 -                              clk_phase[i] = 7;
 -                              break;
 -                      default:
 -                              clk_phase[i] = 0;
 -                              break;
 -                      }
 -              }
 -              hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
 -              regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
 -                      hs_timing);
 -      }
 -      return 0;
 -}
 -
  static struct clk_ops gateclk_ops = {
 -      .prepare = socfpga_clk_prepare,
        .recalc_rate = socfpga_clk_recalc_rate,
        .get_parent = socfpga_clk_get_parent,
        .set_parent = socfpga_clk_set_parent,
@@@ -118,6 -172,7 +118,6 @@@ void __init socfpga_gate_init(struct de
  {
        u32 clk_gate[2];
        u32 div_reg[3];
 -      u32 clk_phase[2];
        u32 fixed_div;
        struct clk_hw *hw_clk;
        struct socfpga_gate_clk *socfpga_clk;
@@@ -133,8 -188,10 +133,10 @@@
                return;
  
        ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
-       if (WARN_ON(!ops))
+       if (WARN_ON(!ops)) {
+               kfree(socfpga_clk);
                return;
+       }
  
        rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
        if (rc)
@@@ -163,6 -220,12 +165,6 @@@
                socfpga_clk->div_reg = NULL;
        }
  
 -      rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
 -      if (!rc) {
 -              socfpga_clk->clk_phase[0] = clk_phase[0];
 -              socfpga_clk->clk_phase[1] = clk_phase[1];
 -      }
 -
        of_property_read_string(node, "clock-output-names", &clk_name);
  
        init.name = clk_name;
@@@ -182,6 -245,7 +184,7 @@@
  
        err = clk_hw_register(NULL, hw_clk);
        if (err) {
+               kfree(ops);
                kfree(socfpga_clk);
                return;
        }