mmc: sdhci_am654: Update delay chain configuration

For speed modes where DLL is not enabled write to TXDLYCLK to enable
transmitter delay chain mode.

Signed-off-by: Faiz Abbas <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ulf Hansson <[email protected]>

diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 8b0f69012d0948e21d699beb1a1d7329dd25eb0b..f7535ee3a23294fe137aa53e1425f9c4594fb9fc 100644 (file)
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -61,6 +61,8 @@
 #define CALDONE_MASK           BIT(CALDONE_SHIFT)
 #define RETRIM_SHIFT           17
 #define RETRIM_MASK            BIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT      17
+#define SELDLYTXCLK_MASK       BIT(SELDLYTXCLK_SHIFT)
 
 #define DRIVER_STRENGTH_50_OHM 0x0
 #define DRIVER_STRENGTH_33_OHM 0x1
@@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
 
        regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 
-       if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ)
+       if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) {
+               regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
+                                  SELDLYTXCLK_MASK, 0);
                sdhci_am654_setup_dll(host, clock);
+       } else {
+               regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
+                                  SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT);
+       }
 }
 
 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,