]> Git Repo - linux.git/commit
spi: stm32: FIFO threshold level - fix align packet size
authorRoman Guskov <[email protected]>
Mon, 21 Dec 2020 12:35:32 +0000 (13:35 +0100)
committerMark Brown <[email protected]>
Mon, 21 Dec 2020 17:18:52 +0000 (17:18 +0000)
commita590370d918fc66c62df6620445791fbe840344a
tree3974e762369f18c4e2ccf7fda522d98d10924327
parent17fa81aa702ec118f2b835715897041675b06336
spi: stm32: FIFO threshold level - fix align packet size

if cur_bpw <= 8 and xfer_len < 4 then the value of fthlv will be 1 and
SPI registers content may have been lost.

* If SPI data register is accessed as a 16-bit register and DSIZE <= 8bit,
  better to select FTHLV = 2, 4, 6 etc

* If SPI data register is accessed as a 32-bit register and DSIZE > 8bit,
  better to select FTHLV = 2, 4, 6 etc, while if DSIZE <= 8bit,
  better to select FTHLV = 4, 8, 12 etc

Signed-off-by: Roman Guskov <[email protected]>
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Reviewed-by: Marek Vasut <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
drivers/spi/spi-stm32.c
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