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clk: sifive: Fix the wrong bit field shift
authorZong Li <[email protected]>
Wed, 9 Dec 2020 09:49:15 +0000 (17:49 +0800)
committerStephen Boyd <[email protected]>
Wed, 16 Dec 2020 20:23:12 +0000 (12:23 -0800)
commit263ac3908516abb0392747bbf595af2b13df5fa2
treefa1e098874aa90289427d2c09b191b59930602f0tree | snapshot
parentefc91ae43c8d4bbf64e4b9a28113b24a74ffd58dcommit | diff
clk: sifive: Fix the wrong bit field shift

The clk enable bit should be 31 instead of 24.

Signed-off-by: Zong Li <[email protected]>
Reported-by: Pragnesh Patel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
drivers/clk/sifive/sifive-prci.h diff | blob | blame | history
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