drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 /* Polaris10/11/12 firmware version */
  41 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
  42
  43 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  44 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  45
  46 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  47 static int uvd_v6_0_start(struct amdgpu_device *adev);
  48 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  49 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  50 static int uvd_v6_0_set_clockgating_state(void *handle,
  51                                           enum amd_clockgating_state state);
  52 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  53                                  bool enable);
  54
  55 /**
  56 * uvd_v6_0_enc_support - get encode support status
  57 *
  58 * @adev: amdgpu_device pointer
  59 *
  60 * Returns the current hardware encode support status
  61 */
  62 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  63 {
  64         return ((adev->asic_type >= CHIP_POLARIS10) &&
  65                         (adev->asic_type <= CHIP_POLARIS12) &&
  66                         (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16));
  67 }
  68
  69 /**
  70  * uvd_v6_0_ring_get_rptr - get read pointer
  71  *
  72  * @ring: amdgpu_ring pointer
  73  *
  74  * Returns the current hardware read pointer
  75  */
  76 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  77 {
  78         struct amdgpu_device *adev = ring->adev;
  79
  80         return RREG32(mmUVD_RBC_RB_RPTR);
  81 }
  82
  83 /**
  84  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  85  *
  86  * @ring: amdgpu_ring pointer
  87  *
  88  * Returns the current hardware enc read pointer
  89  */
  90 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  91 {
  92         struct amdgpu_device *adev = ring->adev;
  93
  94         if (ring == &adev->uvd.ring_enc[0])
  95                 return RREG32(mmUVD_RB_RPTR);
  96         else
  97                 return RREG32(mmUVD_RB_RPTR2);
  98 }
  99 /**
 100  * uvd_v6_0_ring_get_wptr - get write pointer
 101  *
 102  * @ring: amdgpu_ring pointer
 103  *
 104  * Returns the current hardware write pointer
 105  */
 106 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 107 {
 108         struct amdgpu_device *adev = ring->adev;
 109
 110         return RREG32(mmUVD_RBC_RB_WPTR);
 111 }
 112
 113 /**
 114  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 115  *
 116  * @ring: amdgpu_ring pointer
 117  *
 118  * Returns the current hardware enc write pointer
 119  */
 120 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 121 {
 122         struct amdgpu_device *adev = ring->adev;
 123
 124         if (ring == &adev->uvd.ring_enc[0])
 125                 return RREG32(mmUVD_RB_WPTR);
 126         else
 127                 return RREG32(mmUVD_RB_WPTR2);
 128 }
 129
 130 /**
 131  * uvd_v6_0_ring_set_wptr - set write pointer
 132  *
 133  * @ring: amdgpu_ring pointer
 134  *
 135  * Commits the write pointer to the hardware
 136  */
 137 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 138 {
 139         struct amdgpu_device *adev = ring->adev;
 140
 141         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 142 }
 143
 144 /**
 145  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 146  *
 147  * @ring: amdgpu_ring pointer
 148  *
 149  * Commits the enc write pointer to the hardware
 150  */
 151 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 152 {
 153         struct amdgpu_device *adev = ring->adev;
 154
 155         if (ring == &adev->uvd.ring_enc[0])
 156                 WREG32(mmUVD_RB_WPTR,
 157                         lower_32_bits(ring->wptr));
 158         else
 159                 WREG32(mmUVD_RB_WPTR2,
 160                         lower_32_bits(ring->wptr));
 161 }
 162
 163 /**
 164  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 165  *
 166  * @ring: the engine to test on
 167  *
 168  */
 169 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 170 {
 171         struct amdgpu_device *adev = ring->adev;
 172         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 173         unsigned i;
 174         int r;
 175
 176         r = amdgpu_ring_alloc(ring, 16);
 177         if (r) {
 178                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 179                           ring->idx, r);
 180                 return r;
 181         }
 182         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 183         amdgpu_ring_commit(ring);
 184
 185         for (i = 0; i < adev->usec_timeout; i++) {
 186                 if (amdgpu_ring_get_rptr(ring) != rptr)
 187                         break;
 188                 DRM_UDELAY(1);
 189         }
 190
 191         if (i < adev->usec_timeout) {
 192                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 193                          ring->idx, i);
 194         } else {
 195                 DRM_ERROR("amdgpu: ring %d test failed\n",
 196                           ring->idx);
 197                 r = -ETIMEDOUT;
 198         }
 199
 200         return r;
 201 }
 202
 203 /**
 204  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 205  *
 206  * @adev: amdgpu_device pointer
 207  * @ring: ring we should submit the msg to
 208  * @handle: session handle to use
 209  * @fence: optional fence to return
 210  *
 211  * Open up a stream for HW test
 212  */
 213 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 214                                        struct dma_fence **fence)
 215 {
 216         const unsigned ib_size_dw = 16;
 217         struct amdgpu_job *job;
 218         struct amdgpu_ib *ib;
 219         struct dma_fence *f = NULL;
 220         uint64_t dummy;
 221         int i, r;
 222
 223         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 224         if (r)
 225                 return r;
 226
 227         ib = &job->ibs[0];
 228         dummy = ib->gpu_addr + 1024;
 229
 230         ib->length_dw = 0;
 231         ib->ptr[ib->length_dw++] = 0x00000018;
 232         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 233         ib->ptr[ib->length_dw++] = handle;
 234         ib->ptr[ib->length_dw++] = 0x00010000;
 235         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 236         ib->ptr[ib->length_dw++] = dummy;
 237
 238         ib->ptr[ib->length_dw++] = 0x00000014;
 239         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 240         ib->ptr[ib->length_dw++] = 0x0000001c;
 241         ib->ptr[ib->length_dw++] = 0x00000001;
 242         ib->ptr[ib->length_dw++] = 0x00000000;
 243
 244         ib->ptr[ib->length_dw++] = 0x00000008;
 245         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 246
 247         for (i = ib->length_dw; i < ib_size_dw; ++i)
 248                 ib->ptr[i] = 0x0;
 249
 250         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 251         job->fence = dma_fence_get(f);
 252         if (r)
 253                 goto err;
 254
 255         amdgpu_job_free(job);
 256         if (fence)
 257                 *fence = dma_fence_get(f);
 258         dma_fence_put(f);
 259         return 0;
 260
 261 err:
 262         amdgpu_job_free(job);
 263         return r;
 264 }
 265
 266 /**
 267  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 268  *
 269  * @adev: amdgpu_device pointer
 270  * @ring: ring we should submit the msg to
 271  * @handle: session handle to use
 272  * @fence: optional fence to return
 273  *
 274  * Close up a stream for HW test or if userspace failed to do so
 275  */
 276 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 277                                         uint32_t handle,
 278                                         bool direct, struct dma_fence **fence)
 279 {
 280         const unsigned ib_size_dw = 16;
 281         struct amdgpu_job *job;
 282         struct amdgpu_ib *ib;
 283         struct dma_fence *f = NULL;
 284         uint64_t dummy;
 285         int i, r;
 286
 287         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 288         if (r)
 289                 return r;
 290
 291         ib = &job->ibs[0];
 292         dummy = ib->gpu_addr + 1024;
 293
 294         ib->length_dw = 0;
 295         ib->ptr[ib->length_dw++] = 0x00000018;
 296         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 297         ib->ptr[ib->length_dw++] = handle;
 298         ib->ptr[ib->length_dw++] = 0x00010000;
 299         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 300         ib->ptr[ib->length_dw++] = dummy;
 301
 302         ib->ptr[ib->length_dw++] = 0x00000014;
 303         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 304         ib->ptr[ib->length_dw++] = 0x0000001c;
 305         ib->ptr[ib->length_dw++] = 0x00000001;
 306         ib->ptr[ib->length_dw++] = 0x00000000;
 307
 308         ib->ptr[ib->length_dw++] = 0x00000008;
 309         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 310
 311         for (i = ib->length_dw; i < ib_size_dw; ++i)
 312                 ib->ptr[i] = 0x0;
 313
 314         if (direct) {
 315                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 316                 job->fence = dma_fence_get(f);
 317                 if (r)
 318                         goto err;
 319
 320                 amdgpu_job_free(job);
 321         } else {
 322                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 323                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 324                 if (r)
 325                         goto err;
 326         }
 327
 328         if (fence)
 329                 *fence = dma_fence_get(f);
 330         dma_fence_put(f);
 331         return 0;
 332
 333 err:
 334         amdgpu_job_free(job);
 335         return r;
 336 }
 337
 338 /**
 339  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 340  *
 341  * @ring: the engine to test on
 342  *
 343  */
 344 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 345 {
 346         struct dma_fence *fence = NULL;
 347         long r;
 348
 349         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
 350         if (r) {
 351                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 352                 goto error;
 353         }
 354
 355         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
 356         if (r) {
 357                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 358                 goto error;
 359         }
 360
 361         r = dma_fence_wait_timeout(fence, false, timeout);
 362         if (r == 0) {
 363                 DRM_ERROR("amdgpu: IB test timed out.\n");
 364                 r = -ETIMEDOUT;
 365         } else if (r < 0) {
 366                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 367         } else {
 368                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 369                 r = 0;
 370         }
 371 error:
 372         dma_fence_put(fence);
 373         return r;
 374 }
 375 static int uvd_v6_0_early_init(void *handle)
 376 {
 377         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 378
 379         if (!(adev->flags & AMD_IS_APU) &&
 380             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 381                 return -ENOENT;
 382
 383         uvd_v6_0_set_ring_funcs(adev);
 384
 385         if (uvd_v6_0_enc_support(adev)) {
 386                 adev->uvd.num_enc_rings = 2;
 387                 uvd_v6_0_set_enc_ring_funcs(adev);
 388         }
 389
 390         uvd_v6_0_set_irq_funcs(adev);
 391
 392         return 0;
 393 }
 394
 395 static int uvd_v6_0_sw_init(void *handle)
 396 {
 397         struct amdgpu_ring *ring;
 398         int i, r;
 399         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 400
 401         /* UVD TRAP */
 402         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 403         if (r)
 404                 return r;
 405
 406         /* UVD ENC TRAP */
 407         if (uvd_v6_0_enc_support(adev)) {
 408                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 409                         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
 410                         if (r)
 411                                 return r;
 412                 }
 413         }
 414
 415         r = amdgpu_uvd_sw_init(adev);
 416         if (r)
 417                 return r;
 418
 419         if (!uvd_v6_0_enc_support(adev)) {
 420                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 421                         adev->uvd.ring_enc[i].funcs = NULL;
 422
 423                 adev->uvd.irq.num_types = 1;
 424                 adev->uvd.num_enc_rings = 0;
 425
 426                 DRM_INFO("UVD ENC is disabled\n");
 427         } else {
 428                 struct drm_sched_rq *rq;
 429                 ring = &adev->uvd.ring_enc[0];
 430                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 431                 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
 432                                           rq, amdgpu_sched_jobs, NULL);
 433                 if (r) {
 434                         DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 435                         return r;
 436                 }
 437         }
 438
 439         r = amdgpu_uvd_resume(adev);
 440         if (r)
 441                 return r;
 442
 443         ring = &adev->uvd.ring;
 444         sprintf(ring->name, "uvd");
 445         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 446         if (r)
 447                 return r;
 448
 449         if (uvd_v6_0_enc_support(adev)) {
 450                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 451                         ring = &adev->uvd.ring_enc[i];
 452                         sprintf(ring->name, "uvd_enc%d", i);
 453                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 454                         if (r)
 455                                 return r;
 456                 }
 457         }
 458
 459         return r;
 460 }
 461
 462 static int uvd_v6_0_sw_fini(void *handle)
 463 {
 464         int i, r;
 465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 466
 467         r = amdgpu_uvd_suspend(adev);
 468         if (r)
 469                 return r;
 470
 471         if (uvd_v6_0_enc_support(adev)) {
 472                 drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 473
 474                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 475                         amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 476         }
 477
 478         return amdgpu_uvd_sw_fini(adev);
 479 }
 480
 481 /**
 482  * uvd_v6_0_hw_init - start and test UVD block
 483  *
 484  * @adev: amdgpu_device pointer
 485  *
 486  * Initialize the hardware, boot up the VCPU and do some testing
 487  */
 488 static int uvd_v6_0_hw_init(void *handle)
 489 {
 490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 491         struct amdgpu_ring *ring = &adev->uvd.ring;
 492         uint32_t tmp;
 493         int i, r;
 494
 495         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 496         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 497         uvd_v6_0_enable_mgcg(adev, true);
 498
 499         ring->ready = true;
 500         r = amdgpu_ring_test_ring(ring);
 501         if (r) {
 502                 ring->ready = false;
 503                 goto done;
 504         }
 505
 506         r = amdgpu_ring_alloc(ring, 10);
 507         if (r) {
 508                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 509                 goto done;
 510         }
 511
 512         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 513         amdgpu_ring_write(ring, tmp);
 514         amdgpu_ring_write(ring, 0xFFFFF);
 515
 516         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 517         amdgpu_ring_write(ring, tmp);
 518         amdgpu_ring_write(ring, 0xFFFFF);
 519
 520         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 521         amdgpu_ring_write(ring, tmp);
 522         amdgpu_ring_write(ring, 0xFFFFF);
 523
 524         /* Clear timeout status bits */
 525         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 526         amdgpu_ring_write(ring, 0x8);
 527
 528         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 529         amdgpu_ring_write(ring, 3);
 530
 531         amdgpu_ring_commit(ring);
 532
 533         if (uvd_v6_0_enc_support(adev)) {
 534                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 535                         ring = &adev->uvd.ring_enc[i];
 536                         ring->ready = true;
 537                         r = amdgpu_ring_test_ring(ring);
 538                         if (r) {
 539                                 ring->ready = false;
 540                                 goto done;
 541                         }
 542                 }
 543         }
 544
 545 done:
 546         if (!r) {
 547                 if (uvd_v6_0_enc_support(adev))
 548                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 549                 else
 550                         DRM_INFO("UVD initialized successfully.\n");
 551         }
 552
 553         return r;
 554 }
 555
 556 /**
 557  * uvd_v6_0_hw_fini - stop the hardware block
 558  *
 559  * @adev: amdgpu_device pointer
 560  *
 561  * Stop the UVD block, mark ring as not ready any more
 562  */
 563 static int uvd_v6_0_hw_fini(void *handle)
 564 {
 565         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 566         struct amdgpu_ring *ring = &adev->uvd.ring;
 567
 568         if (RREG32(mmUVD_STATUS) != 0)
 569                 uvd_v6_0_stop(adev);
 570
 571         ring->ready = false;
 572
 573         return 0;
 574 }
 575
 576 static int uvd_v6_0_suspend(void *handle)
 577 {
 578         int r;
 579         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 580
 581         r = uvd_v6_0_hw_fini(adev);
 582         if (r)
 583                 return r;
 584
 585         return amdgpu_uvd_suspend(adev);
 586 }
 587
 588 static int uvd_v6_0_resume(void *handle)
 589 {
 590         int r;
 591         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 592
 593         r = amdgpu_uvd_resume(adev);
 594         if (r)
 595                 return r;
 596
 597         return uvd_v6_0_hw_init(adev);
 598 }
 599
 600 /**
 601  * uvd_v6_0_mc_resume - memory controller programming
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Let the UVD memory controller know it's offsets
 606  */
 607 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 608 {
 609         uint64_t offset;
 610         uint32_t size;
 611
 612         /* programm memory controller bits 0-27 */
 613         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 614                         lower_32_bits(adev->uvd.gpu_addr));
 615         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 616                         upper_32_bits(adev->uvd.gpu_addr));
 617
 618         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 619         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 620         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 621         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 622
 623         offset += size;
 624         size = AMDGPU_UVD_HEAP_SIZE;
 625         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 626         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 627
 628         offset += size;
 629         size = AMDGPU_UVD_STACK_SIZE +
 630                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 631         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 632         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 633
 634         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 635         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 636         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 637
 638         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 639 }
 640
 641 #if 0
 642 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 643                 bool enable)
 644 {
 645         u32 data, data1;
 646
 647         data = RREG32(mmUVD_CGC_GATE);
 648         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 649         if (enable) {
 650                 data |= UVD_CGC_GATE__SYS_MASK |
 651                                 UVD_CGC_GATE__UDEC_MASK |
 652                                 UVD_CGC_GATE__MPEG2_MASK |
 653                                 UVD_CGC_GATE__RBC_MASK |
 654                                 UVD_CGC_GATE__LMI_MC_MASK |
 655                                 UVD_CGC_GATE__IDCT_MASK |
 656                                 UVD_CGC_GATE__MPRD_MASK |
 657                                 UVD_CGC_GATE__MPC_MASK |
 658                                 UVD_CGC_GATE__LBSI_MASK |
 659                                 UVD_CGC_GATE__LRBBM_MASK |
 660                                 UVD_CGC_GATE__UDEC_RE_MASK |
 661                                 UVD_CGC_GATE__UDEC_CM_MASK |
 662                                 UVD_CGC_GATE__UDEC_IT_MASK |
 663                                 UVD_CGC_GATE__UDEC_DB_MASK |
 664                                 UVD_CGC_GATE__UDEC_MP_MASK |
 665                                 UVD_CGC_GATE__WCB_MASK |
 666                                 UVD_CGC_GATE__VCPU_MASK |
 667                                 UVD_CGC_GATE__SCPU_MASK;
 668                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 669                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 670                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 671                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 672                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 673                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 674                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 675                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 676                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 677                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 678                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 679                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 680                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 681         } else {
 682                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 683                                 UVD_CGC_GATE__UDEC_MASK |
 684                                 UVD_CGC_GATE__MPEG2_MASK |
 685                                 UVD_CGC_GATE__RBC_MASK |
 686                                 UVD_CGC_GATE__LMI_MC_MASK |
 687                                 UVD_CGC_GATE__LMI_UMC_MASK |
 688                                 UVD_CGC_GATE__IDCT_MASK |
 689                                 UVD_CGC_GATE__MPRD_MASK |
 690                                 UVD_CGC_GATE__MPC_MASK |
 691                                 UVD_CGC_GATE__LBSI_MASK |
 692                                 UVD_CGC_GATE__LRBBM_MASK |
 693                                 UVD_CGC_GATE__UDEC_RE_MASK |
 694                                 UVD_CGC_GATE__UDEC_CM_MASK |
 695                                 UVD_CGC_GATE__UDEC_IT_MASK |
 696                                 UVD_CGC_GATE__UDEC_DB_MASK |
 697                                 UVD_CGC_GATE__UDEC_MP_MASK |
 698                                 UVD_CGC_GATE__WCB_MASK |
 699                                 UVD_CGC_GATE__VCPU_MASK |
 700                                 UVD_CGC_GATE__SCPU_MASK);
 701                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 702                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 703                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 704                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 705                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 706                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 707                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 708                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 709                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 710                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 711                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 712                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 713                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 714         }
 715         WREG32(mmUVD_CGC_GATE, data);
 716         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 717 }
 718 #endif
 719
 720 /**
 721  * uvd_v6_0_start - start UVD block
 722  *
 723  * @adev: amdgpu_device pointer
 724  *
 725  * Setup and start the UVD block
 726  */
 727 static int uvd_v6_0_start(struct amdgpu_device *adev)
 728 {
 729         struct amdgpu_ring *ring = &adev->uvd.ring;
 730         uint32_t rb_bufsz, tmp;
 731         uint32_t lmi_swap_cntl;
 732         uint32_t mp_swap_cntl;
 733         int i, j, r;
 734
 735         /* disable DPG */
 736         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 737
 738         /* disable byte swapping */
 739         lmi_swap_cntl = 0;
 740         mp_swap_cntl = 0;
 741
 742         uvd_v6_0_mc_resume(adev);
 743
 744         /* disable interupt */
 745         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 746
 747         /* stall UMC and register bus before resetting VCPU */
 748         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 749         mdelay(1);
 750
 751         /* put LMI, VCPU, RBC etc... into reset */
 752         WREG32(mmUVD_SOFT_RESET,
 753                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 754                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 755                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 756                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 757                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 758                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 759                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 760                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 761         mdelay(5);
 762
 763         /* take UVD block out of reset */
 764         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 765         mdelay(5);
 766
 767         /* initialize UVD memory controller */
 768         WREG32(mmUVD_LMI_CTRL,
 769                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 770                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 771                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 772                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 773                 UVD_LMI_CTRL__REQ_MODE_MASK |
 774                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 775
 776 #ifdef __BIG_ENDIAN
 777         /* swap (8 in 32) RB and IB */
 778         lmi_swap_cntl = 0xa;
 779         mp_swap_cntl = 0;
 780 #endif
 781         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 782         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 783
 784         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 785         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 786         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 787         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 788         WREG32(mmUVD_MPC_SET_ALU, 0);
 789         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 790
 791         /* take all subblocks out of reset, except VCPU */
 792         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 793         mdelay(5);
 794
 795         /* enable VCPU clock */
 796         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 797
 798         /* enable UMC */
 799         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 800
 801         /* boot up the VCPU */
 802         WREG32(mmUVD_SOFT_RESET, 0);
 803         mdelay(10);
 804
 805         for (i = 0; i < 10; ++i) {
 806                 uint32_t status;
 807
 808                 for (j = 0; j < 100; ++j) {
 809                         status = RREG32(mmUVD_STATUS);
 810                         if (status & 2)
 811                                 break;
 812                         mdelay(10);
 813                 }
 814                 r = 0;
 815                 if (status & 2)
 816                         break;
 817
 818                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 819                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 820                 mdelay(10);
 821                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 822                 mdelay(10);
 823                 r = -1;
 824         }
 825
 826         if (r) {
 827                 DRM_ERROR("UVD not responding, giving up!!!\n");
 828                 return r;
 829         }
 830         /* enable master interrupt */
 831         WREG32_P(mmUVD_MASTINT_EN,
 832                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 833                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 834
 835         /* clear the bit 4 of UVD_STATUS */
 836         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 837
 838         /* force RBC into idle state */
 839         rb_bufsz = order_base_2(ring->ring_size);
 840         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 841         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 842         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 843         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 844         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 845         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 846         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 847
 848         /* set the write pointer delay */
 849         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 850
 851         /* set the wb address */
 852         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 853
 854         /* programm the RB_BASE for ring buffer */
 855         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 856                         lower_32_bits(ring->gpu_addr));
 857         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 858                         upper_32_bits(ring->gpu_addr));
 859
 860         /* Initialize the ring buffer's read and write pointers */
 861         WREG32(mmUVD_RBC_RB_RPTR, 0);
 862
 863         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 864         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 865
 866         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 867
 868         if (uvd_v6_0_enc_support(adev)) {
 869                 ring = &adev->uvd.ring_enc[0];
 870                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 871                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 872                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 873                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 874                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 875
 876                 ring = &adev->uvd.ring_enc[1];
 877                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 878                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 879                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 880                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 881                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 882         }
 883
 884         return 0;
 885 }
 886
 887 /**
 888  * uvd_v6_0_stop - stop UVD block
 889  *
 890  * @adev: amdgpu_device pointer
 891  *
 892  * stop the UVD block
 893  */
 894 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 895 {
 896         /* force RBC into idle state */
 897         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 898
 899         /* Stall UMC and register bus before resetting VCPU */
 900         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 901         mdelay(1);
 902
 903         /* put VCPU into reset */
 904         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 905         mdelay(5);
 906
 907         /* disable VCPU clock */
 908         WREG32(mmUVD_VCPU_CNTL, 0x0);
 909
 910         /* Unstall UMC and register bus */
 911         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 912
 913         WREG32(mmUVD_STATUS, 0);
 914 }
 915
 916 /**
 917  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 918  *
 919  * @ring: amdgpu_ring pointer
 920  * @fence: fence to emit
 921  *
 922  * Write a fence and a trap command to the ring.
 923  */
 924 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 925                                      unsigned flags)
 926 {
 927         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 928
 929         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 930         amdgpu_ring_write(ring, seq);
 931         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 932         amdgpu_ring_write(ring, addr & 0xffffffff);
 933         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 934         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 935         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 936         amdgpu_ring_write(ring, 0);
 937
 938         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 939         amdgpu_ring_write(ring, 0);
 940         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 941         amdgpu_ring_write(ring, 0);
 942         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 943         amdgpu_ring_write(ring, 2);
 944 }
 945
 946 /**
 947  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 948  *
 949  * @ring: amdgpu_ring pointer
 950  * @fence: fence to emit
 951  *
 952  * Write enc a fence and a trap command to the ring.
 953  */
 954 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 955                         u64 seq, unsigned flags)
 956 {
 957         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 958
 959         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 960         amdgpu_ring_write(ring, addr);
 961         amdgpu_ring_write(ring, upper_32_bits(addr));
 962         amdgpu_ring_write(ring, seq);
 963         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 964 }
 965
 966 /**
 967  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 968  *
 969  * @ring: amdgpu_ring pointer
 970  *
 971  * Emits an hdp flush.
 972  */
 973 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 974 {
 975         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 976         amdgpu_ring_write(ring, 0);
 977 }
 978
 979 /**
 980  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 981  *
 982  * @ring: amdgpu_ring pointer
 983  *
 984  * Emits an hdp invalidate.
 985  */
 986 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 987 {
 988         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 989         amdgpu_ring_write(ring, 1);
 990 }
 991
 992 /**
 993  * uvd_v6_0_ring_test_ring - register write test
 994  *
 995  * @ring: amdgpu_ring pointer
 996  *
 997  * Test if we can successfully write to the context register
 998  */
 999 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1000 {
1001         struct amdgpu_device *adev = ring->adev;
1002         uint32_t tmp = 0;
1003         unsigned i;
1004         int r;
1005
1006         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1007         r = amdgpu_ring_alloc(ring, 3);
1008         if (r) {
1009                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1010                           ring->idx, r);
1011                 return r;
1012         }
1013         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
1014         amdgpu_ring_write(ring, 0xDEADBEEF);
1015         amdgpu_ring_commit(ring);
1016         for (i = 0; i < adev->usec_timeout; i++) {
1017                 tmp = RREG32(mmUVD_CONTEXT_ID);
1018                 if (tmp == 0xDEADBEEF)
1019                         break;
1020                 DRM_UDELAY(1);
1021         }
1022
1023         if (i < adev->usec_timeout) {
1024                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1025                          ring->idx, i);
1026         } else {
1027                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1028                           ring->idx, tmp);
1029                 r = -EINVAL;
1030         }
1031         return r;
1032 }
1033
1034 /**
1035  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1036  *
1037  * @ring: amdgpu_ring pointer
1038  * @ib: indirect buffer to execute
1039  *
1040  * Write ring commands to execute the indirect buffer
1041  */
1042 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1043                                   struct amdgpu_ib *ib,
1044                                   unsigned vmid, bool ctx_switch)
1045 {
1046         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1047         amdgpu_ring_write(ring, vmid);
1048
1049         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1050         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1051         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1052         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1053         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1054         amdgpu_ring_write(ring, ib->length_dw);
1055 }
1056
1057 /**
1058  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1059  *
1060  * @ring: amdgpu_ring pointer
1061  * @ib: indirect buffer to execute
1062  *
1063  * Write enc ring commands to execute the indirect buffer
1064  */
1065 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1066                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1067 {
1068         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1069         amdgpu_ring_write(ring, vmid);
1070         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1071         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1072         amdgpu_ring_write(ring, ib->length_dw);
1073 }
1074
1075 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1076                                          unsigned vmid, uint64_t pd_addr)
1077 {
1078         uint32_t reg;
1079
1080         if (vmid < 8)
1081                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
1082         else
1083                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
1084
1085         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1086         amdgpu_ring_write(ring, reg << 2);
1087         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1088         amdgpu_ring_write(ring, pd_addr >> 12);
1089         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1090         amdgpu_ring_write(ring, 0x8);
1091
1092         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1093         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1094         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1095         amdgpu_ring_write(ring, 1 << vmid);
1096         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1097         amdgpu_ring_write(ring, 0x8);
1098
1099         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1100         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1101         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1102         amdgpu_ring_write(ring, 0);
1103         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1104         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1105         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1106         amdgpu_ring_write(ring, 0xC);
1107 }
1108
1109 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1110 {
1111         uint32_t seq = ring->fence_drv.sync_seq;
1112         uint64_t addr = ring->fence_drv.gpu_addr;
1113
1114         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1115         amdgpu_ring_write(ring, lower_32_bits(addr));
1116         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1117         amdgpu_ring_write(ring, upper_32_bits(addr));
1118         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1119         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1120         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1121         amdgpu_ring_write(ring, seq);
1122         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1123         amdgpu_ring_write(ring, 0xE);
1124 }
1125
1126 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1127 {
1128         uint32_t seq = ring->fence_drv.sync_seq;
1129         uint64_t addr = ring->fence_drv.gpu_addr;
1130
1131         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1132         amdgpu_ring_write(ring, lower_32_bits(addr));
1133         amdgpu_ring_write(ring, upper_32_bits(addr));
1134         amdgpu_ring_write(ring, seq);
1135 }
1136
1137 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1138 {
1139         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1140 }
1141
1142 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1143         unsigned int vmid, uint64_t pd_addr)
1144 {
1145         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1146         amdgpu_ring_write(ring, vmid);
1147         amdgpu_ring_write(ring, pd_addr >> 12);
1148
1149         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1150         amdgpu_ring_write(ring, vmid);
1151 }
1152
1153 static bool uvd_v6_0_is_idle(void *handle)
1154 {
1155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1158 }
1159
1160 static int uvd_v6_0_wait_for_idle(void *handle)
1161 {
1162         unsigned i;
1163         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1164
1165         for (i = 0; i < adev->usec_timeout; i++) {
1166                 if (uvd_v6_0_is_idle(handle))
1167                         return 0;
1168         }
1169         return -ETIMEDOUT;
1170 }
1171
1172 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1173 static bool uvd_v6_0_check_soft_reset(void *handle)
1174 {
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176         u32 srbm_soft_reset = 0;
1177         u32 tmp = RREG32(mmSRBM_STATUS);
1178
1179         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1180             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1181             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1182                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1183
1184         if (srbm_soft_reset) {
1185                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1186                 return true;
1187         } else {
1188                 adev->uvd.srbm_soft_reset = 0;
1189                 return false;
1190         }
1191 }
1192
1193 static int uvd_v6_0_pre_soft_reset(void *handle)
1194 {
1195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197         if (!adev->uvd.srbm_soft_reset)
1198                 return 0;
1199
1200         uvd_v6_0_stop(adev);
1201         return 0;
1202 }
1203
1204 static int uvd_v6_0_soft_reset(void *handle)
1205 {
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207         u32 srbm_soft_reset;
1208
1209         if (!adev->uvd.srbm_soft_reset)
1210                 return 0;
1211         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1212
1213         if (srbm_soft_reset) {
1214                 u32 tmp;
1215
1216                 tmp = RREG32(mmSRBM_SOFT_RESET);
1217                 tmp |= srbm_soft_reset;
1218                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1219                 WREG32(mmSRBM_SOFT_RESET, tmp);
1220                 tmp = RREG32(mmSRBM_SOFT_RESET);
1221
1222                 udelay(50);
1223
1224                 tmp &= ~srbm_soft_reset;
1225                 WREG32(mmSRBM_SOFT_RESET, tmp);
1226                 tmp = RREG32(mmSRBM_SOFT_RESET);
1227
1228                 /* Wait a little for things to settle down */
1229                 udelay(50);
1230         }
1231
1232         return 0;
1233 }
1234
1235 static int uvd_v6_0_post_soft_reset(void *handle)
1236 {
1237         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238
1239         if (!adev->uvd.srbm_soft_reset)
1240                 return 0;
1241
1242         mdelay(5);
1243
1244         return uvd_v6_0_start(adev);
1245 }
1246
1247 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1248                                         struct amdgpu_irq_src *source,
1249                                         unsigned type,
1250                                         enum amdgpu_interrupt_state state)
1251 {
1252         // TODO
1253         return 0;
1254 }
1255
1256 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1257                                       struct amdgpu_irq_src *source,
1258                                       struct amdgpu_iv_entry *entry)
1259 {
1260         bool int_handled = true;
1261         DRM_DEBUG("IH: UVD TRAP\n");
1262
1263         switch (entry->src_id) {
1264         case 124:
1265                 amdgpu_fence_process(&adev->uvd.ring);
1266                 break;
1267         case 119:
1268                 if (likely(uvd_v6_0_enc_support(adev)))
1269                         amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1270                 else
1271                         int_handled = false;
1272                 break;
1273         case 120:
1274                 if (likely(uvd_v6_0_enc_support(adev)))
1275                         amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1276                 else
1277                         int_handled = false;
1278                 break;
1279         }
1280
1281         if (false == int_handled)
1282                         DRM_ERROR("Unhandled interrupt: %d %d\n",
1283                           entry->src_id, entry->src_data[0]);
1284
1285         return 0;
1286 }
1287
1288 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1289 {
1290         uint32_t data1, data3;
1291
1292         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1293         data3 = RREG32(mmUVD_CGC_GATE);
1294
1295         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1296                      UVD_SUVD_CGC_GATE__SIT_MASK |
1297                      UVD_SUVD_CGC_GATE__SMP_MASK |
1298                      UVD_SUVD_CGC_GATE__SCM_MASK |
1299                      UVD_SUVD_CGC_GATE__SDB_MASK |
1300                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1301                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1302                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1303                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1304                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1305                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1306                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1307                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1308
1309         if (enable) {
1310                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1311                         UVD_CGC_GATE__UDEC_MASK      |
1312                         UVD_CGC_GATE__MPEG2_MASK     |
1313                         UVD_CGC_GATE__RBC_MASK       |
1314                         UVD_CGC_GATE__LMI_MC_MASK    |
1315                         UVD_CGC_GATE__LMI_UMC_MASK   |
1316                         UVD_CGC_GATE__IDCT_MASK      |
1317                         UVD_CGC_GATE__MPRD_MASK      |
1318                         UVD_CGC_GATE__MPC_MASK       |
1319                         UVD_CGC_GATE__LBSI_MASK      |
1320                         UVD_CGC_GATE__LRBBM_MASK     |
1321                         UVD_CGC_GATE__UDEC_RE_MASK   |
1322                         UVD_CGC_GATE__UDEC_CM_MASK   |
1323                         UVD_CGC_GATE__UDEC_IT_MASK   |
1324                         UVD_CGC_GATE__UDEC_DB_MASK   |
1325                         UVD_CGC_GATE__UDEC_MP_MASK   |
1326                         UVD_CGC_GATE__WCB_MASK       |
1327                         UVD_CGC_GATE__JPEG_MASK      |
1328                         UVD_CGC_GATE__SCPU_MASK      |
1329                         UVD_CGC_GATE__JPEG2_MASK);
1330                 /* only in pg enabled, we can gate clock to vcpu*/
1331                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1332                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1333
1334                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1335         } else {
1336                 data3 = 0;
1337         }
1338
1339         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1340         WREG32(mmUVD_CGC_GATE, data3);
1341 }
1342
1343 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1344 {
1345         uint32_t data, data2;
1346
1347         data = RREG32(mmUVD_CGC_CTRL);
1348         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1349
1350
1351         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1352                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1353
1354
1355         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1356                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1357                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1358
1359         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1360                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1361                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1362                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1363                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1364                         UVD_CGC_CTRL__SYS_MODE_MASK |
1365                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1366                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1367                         UVD_CGC_CTRL__REGS_MODE_MASK |
1368                         UVD_CGC_CTRL__RBC_MODE_MASK |
1369                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1370                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1371                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1372                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1373                         UVD_CGC_CTRL__MPC_MODE_MASK |
1374                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1375                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1376                         UVD_CGC_CTRL__WCB_MODE_MASK |
1377                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1378                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1379                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1380                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1381         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1382                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1383                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1384                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1385                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1386
1387         WREG32(mmUVD_CGC_CTRL, data);
1388         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1389 }
1390
1391 #if 0
1392 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1393 {
1394         uint32_t data, data1, cgc_flags, suvd_flags;
1395
1396         data = RREG32(mmUVD_CGC_GATE);
1397         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1398
1399         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1400                 UVD_CGC_GATE__UDEC_MASK |
1401                 UVD_CGC_GATE__MPEG2_MASK |
1402                 UVD_CGC_GATE__RBC_MASK |
1403                 UVD_CGC_GATE__LMI_MC_MASK |
1404                 UVD_CGC_GATE__IDCT_MASK |
1405                 UVD_CGC_GATE__MPRD_MASK |
1406                 UVD_CGC_GATE__MPC_MASK |
1407                 UVD_CGC_GATE__LBSI_MASK |
1408                 UVD_CGC_GATE__LRBBM_MASK |
1409                 UVD_CGC_GATE__UDEC_RE_MASK |
1410                 UVD_CGC_GATE__UDEC_CM_MASK |
1411                 UVD_CGC_GATE__UDEC_IT_MASK |
1412                 UVD_CGC_GATE__UDEC_DB_MASK |
1413                 UVD_CGC_GATE__UDEC_MP_MASK |
1414                 UVD_CGC_GATE__WCB_MASK |
1415                 UVD_CGC_GATE__VCPU_MASK |
1416                 UVD_CGC_GATE__SCPU_MASK |
1417                 UVD_CGC_GATE__JPEG_MASK |
1418                 UVD_CGC_GATE__JPEG2_MASK;
1419
1420         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1421                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1422                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1423                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1424                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1425
1426         data |= cgc_flags;
1427         data1 |= suvd_flags;
1428
1429         WREG32(mmUVD_CGC_GATE, data);
1430         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1431 }
1432 #endif
1433
1434 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1435                                  bool enable)
1436 {
1437         u32 orig, data;
1438
1439         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1440                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1441                 data |= 0xfff;
1442                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1443
1444                 orig = data = RREG32(mmUVD_CGC_CTRL);
1445                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1446                 if (orig != data)
1447                         WREG32(mmUVD_CGC_CTRL, data);
1448         } else {
1449                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1450                 data &= ~0xfff;
1451                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1452
1453                 orig = data = RREG32(mmUVD_CGC_CTRL);
1454                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1455                 if (orig != data)
1456                         WREG32(mmUVD_CGC_CTRL, data);
1457         }
1458 }
1459
1460 static int uvd_v6_0_set_clockgating_state(void *handle,
1461                                           enum amd_clockgating_state state)
1462 {
1463         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1464         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1465
1466         if (enable) {
1467                 /* wait for STATUS to clear */
1468                 if (uvd_v6_0_wait_for_idle(handle))
1469                         return -EBUSY;
1470                 uvd_v6_0_enable_clock_gating(adev, true);
1471                 /* enable HW gates because UVD is idle */
1472 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1473         } else {
1474                 /* disable HW gating and enable Sw gating */
1475                 uvd_v6_0_enable_clock_gating(adev, false);
1476         }
1477         uvd_v6_0_set_sw_clock_gating(adev);
1478         return 0;
1479 }
1480
1481 static int uvd_v6_0_set_powergating_state(void *handle,
1482                                           enum amd_powergating_state state)
1483 {
1484         /* This doesn't actually powergate the UVD block.
1485          * That's done in the dpm code via the SMC.  This
1486          * just re-inits the block as necessary.  The actual
1487          * gating still happens in the dpm code.  We should
1488          * revisit this when there is a cleaner line between
1489          * the smc and the hw blocks
1490          */
1491         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1492         int ret = 0;
1493
1494         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1495
1496         if (state == AMD_PG_STATE_GATE) {
1497                 uvd_v6_0_stop(adev);
1498         } else {
1499                 ret = uvd_v6_0_start(adev);
1500                 if (ret)
1501                         goto out;
1502         }
1503
1504 out:
1505         return ret;
1506 }
1507
1508 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1509 {
1510         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1511         int data;
1512
1513         mutex_lock(&adev->pm.mutex);
1514
1515         if (adev->flags & AMD_IS_APU)
1516                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1517         else
1518                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1519
1520         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1521                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1522                 goto out;
1523         }
1524
1525         /* AMD_CG_SUPPORT_UVD_MGCG */
1526         data = RREG32(mmUVD_CGC_CTRL);
1527         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1528                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1529
1530 out:
1531         mutex_unlock(&adev->pm.mutex);
1532 }
1533
1534 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1535         .name = "uvd_v6_0",
1536         .early_init = uvd_v6_0_early_init,
1537         .late_init = NULL,
1538         .sw_init = uvd_v6_0_sw_init,
1539         .sw_fini = uvd_v6_0_sw_fini,
1540         .hw_init = uvd_v6_0_hw_init,
1541         .hw_fini = uvd_v6_0_hw_fini,
1542         .suspend = uvd_v6_0_suspend,
1543         .resume = uvd_v6_0_resume,
1544         .is_idle = uvd_v6_0_is_idle,
1545         .wait_for_idle = uvd_v6_0_wait_for_idle,
1546         .check_soft_reset = uvd_v6_0_check_soft_reset,
1547         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1548         .soft_reset = uvd_v6_0_soft_reset,
1549         .post_soft_reset = uvd_v6_0_post_soft_reset,
1550         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1551         .set_powergating_state = uvd_v6_0_set_powergating_state,
1552         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1553 };
1554
1555 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1556         .type = AMDGPU_RING_TYPE_UVD,
1557         .align_mask = 0xf,
1558         .nop = PACKET0(mmUVD_NO_OP, 0),
1559         .support_64bit_ptrs = false,
1560         .get_rptr = uvd_v6_0_ring_get_rptr,
1561         .get_wptr = uvd_v6_0_ring_get_wptr,
1562         .set_wptr = uvd_v6_0_ring_set_wptr,
1563         .parse_cs = amdgpu_uvd_ring_parse_cs,
1564         .emit_frame_size =
1565                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1566                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1567                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1568                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1569         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1570         .emit_ib = uvd_v6_0_ring_emit_ib,
1571         .emit_fence = uvd_v6_0_ring_emit_fence,
1572         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1573         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1574         .test_ring = uvd_v6_0_ring_test_ring,
1575         .test_ib = amdgpu_uvd_ring_test_ib,
1576         .insert_nop = amdgpu_ring_insert_nop,
1577         .pad_ib = amdgpu_ring_generic_pad_ib,
1578         .begin_use = amdgpu_uvd_ring_begin_use,
1579         .end_use = amdgpu_uvd_ring_end_use,
1580 };
1581
1582 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1583         .type = AMDGPU_RING_TYPE_UVD,
1584         .align_mask = 0xf,
1585         .nop = PACKET0(mmUVD_NO_OP, 0),
1586         .support_64bit_ptrs = false,
1587         .get_rptr = uvd_v6_0_ring_get_rptr,
1588         .get_wptr = uvd_v6_0_ring_get_wptr,
1589         .set_wptr = uvd_v6_0_ring_set_wptr,
1590         .emit_frame_size =
1591                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1592                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1593                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1594                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1595                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1596         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1597         .emit_ib = uvd_v6_0_ring_emit_ib,
1598         .emit_fence = uvd_v6_0_ring_emit_fence,
1599         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1600         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1601         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1602         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1603         .test_ring = uvd_v6_0_ring_test_ring,
1604         .test_ib = amdgpu_uvd_ring_test_ib,
1605         .insert_nop = amdgpu_ring_insert_nop,
1606         .pad_ib = amdgpu_ring_generic_pad_ib,
1607         .begin_use = amdgpu_uvd_ring_begin_use,
1608         .end_use = amdgpu_uvd_ring_end_use,
1609 };
1610
1611 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1612         .type = AMDGPU_RING_TYPE_UVD_ENC,
1613         .align_mask = 0x3f,
1614         .nop = HEVC_ENC_CMD_NO_OP,
1615         .support_64bit_ptrs = false,
1616         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1617         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1618         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1619         .emit_frame_size =
1620                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1621                 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1622                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1623                 1, /* uvd_v6_0_enc_ring_insert_end */
1624         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1625         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1626         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1627         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1628         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1629         .test_ring = uvd_v6_0_enc_ring_test_ring,
1630         .test_ib = uvd_v6_0_enc_ring_test_ib,
1631         .insert_nop = amdgpu_ring_insert_nop,
1632         .insert_end = uvd_v6_0_enc_ring_insert_end,
1633         .pad_ib = amdgpu_ring_generic_pad_ib,
1634         .begin_use = amdgpu_uvd_ring_begin_use,
1635         .end_use = amdgpu_uvd_ring_end_use,
1636 };
1637
1638 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1639 {
1640         if (adev->asic_type >= CHIP_POLARIS10) {
1641                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1642                 DRM_INFO("UVD is enabled in VM mode\n");
1643         } else {
1644                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1645                 DRM_INFO("UVD is enabled in physical mode\n");
1646         }
1647 }
1648
1649 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1650 {
1651         int i;
1652
1653         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1654                 adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1655
1656         DRM_INFO("UVD ENC is enabled in VM mode\n");
1657 }
1658
1659 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1660         .set = uvd_v6_0_set_interrupt_state,
1661         .process = uvd_v6_0_process_interrupt,
1662 };
1663
1664 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1665 {
1666         if (uvd_v6_0_enc_support(adev))
1667                 adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1668         else
1669                 adev->uvd.irq.num_types = 1;
1670
1671         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1672 }
1673
1674 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1675 {
1676                 .type = AMD_IP_BLOCK_TYPE_UVD,
1677                 .major = 6,
1678                 .minor = 0,
1679                 .rev = 0,
1680                 .funcs = &uvd_v6_0_ip_funcs,
1681 };
1682
1683 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1684 {
1685                 .type = AMD_IP_BLOCK_TYPE_UVD,
1686                 .major = 6,
1687                 .minor = 2,
1688                 .rev = 0,
1689                 .funcs = &uvd_v6_0_ip_funcs,
1690 };
1691
1692 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1693 {
1694                 .type = AMD_IP_BLOCK_TYPE_UVD,
1695                 .major = 6,
1696                 .minor = 3,
1697                 .rev = 0,
1698                 .funcs = &uvd_v6_0_ip_funcs,
1699 };