drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include "dc.h"
  20 #include "drm.h"
  21 #include "gem.h"
  22 #include "hub.h"
  23 #include "plane.h"
  24
  25 #include <drm/drm_atomic.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_plane_helper.h>
  28
  29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  30 {
  31         stats->frames = 0;
  32         stats->vblank = 0;
  33         stats->underflow = 0;
  34         stats->overflow = 0;
  35 }
  36
  37 /* Reads the active copy of a register. */
  38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  39 {
  40         u32 value;
  41
  42         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  43         value = tegra_dc_readl(dc, offset);
  44         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  45
  46         return value;
  47 }
  48
  49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
  50                                               unsigned int offset)
  51 {
  52         if (offset >= 0x500 && offset <= 0x638) {
  53                 offset = 0x000 + (offset - 0x500);
  54                 return plane->offset + offset;
  55         }
  56
  57         if (offset >= 0x700 && offset <= 0x719) {
  58                 offset = 0x180 + (offset - 0x700);
  59                 return plane->offset + offset;
  60         }
  61
  62         if (offset >= 0x800 && offset <= 0x839) {
  63                 offset = 0x1c0 + (offset - 0x800);
  64                 return plane->offset + offset;
  65         }
  66
  67         dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
  68
  69         return plane->offset + offset;
  70 }
  71
  72 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
  73                                     unsigned int offset)
  74 {
  75         return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
  76 }
  77
  78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
  79                                       unsigned int offset)
  80 {
  81         tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
  82 }
  83
  84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
  85 {
  86         struct device_node *np = dc->dev->of_node;
  87         struct of_phandle_iterator it;
  88         int err;
  89
  90         of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
  91                 if (it.node == dev->of_node)
  92                         return true;
  93
  94         return false;
  95 }
  96
  97 /*
  98  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
  99  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 100  * Latching happens mmediately if the display controller is in STOP mode or
 101  * on the next frame boundary otherwise.
 102  *
 103  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 104  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 105  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 106  * into the ACTIVE copy, either immediately if the display controller is in
 107  * STOP mode, or at the next frame boundary otherwise.
 108  */
 109 void tegra_dc_commit(struct tegra_dc *dc)
 110 {
 111         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 112         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 113 }
 114
 115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 116                                   unsigned int bpp)
 117 {
 118         fixed20_12 outf = dfixed_init(out);
 119         fixed20_12 inf = dfixed_init(in);
 120         u32 dda_inc;
 121         int max;
 122
 123         if (v)
 124                 max = 15;
 125         else {
 126                 switch (bpp) {
 127                 case 2:
 128                         max = 8;
 129                         break;
 130
 131                 default:
 132                         WARN_ON_ONCE(1);
 133                         /* fallthrough */
 134                 case 4:
 135                         max = 4;
 136                         break;
 137                 }
 138         }
 139
 140         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 141         inf.full -= dfixed_const(1);
 142
 143         dda_inc = dfixed_div(inf, outf);
 144         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 145
 146         return dda_inc;
 147 }
 148
 149 static inline u32 compute_initial_dda(unsigned int in)
 150 {
 151         fixed20_12 inf = dfixed_init(in);
 152         return dfixed_frac(inf);
 153 }
 154
 155 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
 156 {
 157         u32 background[3] = {
 158                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 159                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 160                 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
 161         };
 162         u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
 163                          BLEND_COLOR_KEY_NONE;
 164         u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
 165         struct tegra_plane_state *state;
 166         u32 blending[2];
 167         unsigned int i;
 168
 169         /* disable blending for non-overlapping case */
 170         tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
 171         tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
 172
 173         state = to_tegra_plane_state(plane->base.state);
 174
 175         if (state->opaque) {
 176                 /*
 177                  * Since custom fix-weight blending isn't utilized and weight
 178                  * of top window is set to max, we can enforce dependent
 179                  * blending which in this case results in transparent bottom
 180                  * window if top window is opaque and if top window enables
 181                  * alpha blending, then bottom window is getting alpha value
 182                  * of 1 minus the sum of alpha components of the overlapping
 183                  * plane.
 184                  */
 185                 background[0] |= BLEND_CONTROL_DEPENDENT;
 186                 background[1] |= BLEND_CONTROL_DEPENDENT;
 187
 188                 /*
 189                  * The region where three windows overlap is the intersection
 190                  * of the two regions where two windows overlap. It contributes
 191                  * to the area if all of the windows on top of it have an alpha
 192                  * component.
 193                  */
 194                 switch (state->base.normalized_zpos) {
 195                 case 0:
 196                         if (state->blending[0].alpha &&
 197                             state->blending[1].alpha)
 198                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 199                         break;
 200
 201                 case 1:
 202                         background[2] |= BLEND_CONTROL_DEPENDENT;
 203                         break;
 204                 }
 205         } else {
 206                 /*
 207                  * Enable alpha blending if pixel format has an alpha
 208                  * component.
 209                  */
 210                 foreground |= BLEND_CONTROL_ALPHA;
 211
 212                 /*
 213                  * If any of the windows on top of this window is opaque, it
 214                  * will completely conceal this window within that area. If
 215                  * top window has an alpha component, it is blended over the
 216                  * bottom window.
 217                  */
 218                 for (i = 0; i < 2; i++) {
 219                         if (state->blending[i].alpha &&
 220                             state->blending[i].top)
 221                                 background[i] |= BLEND_CONTROL_DEPENDENT;
 222                 }
 223
 224                 switch (state->base.normalized_zpos) {
 225                 case 0:
 226                         if (state->blending[0].alpha &&
 227                             state->blending[1].alpha)
 228                                 background[2] |= BLEND_CONTROL_DEPENDENT;
 229                         break;
 230
 231                 case 1:
 232                         /*
 233                          * When both middle and topmost windows have an alpha,
 234                          * these windows a mixed together and then the result
 235                          * is blended over the bottom window.
 236                          */
 237                         if (state->blending[0].alpha &&
 238                             state->blending[0].top)
 239                                 background[2] |= BLEND_CONTROL_ALPHA;
 240
 241                         if (state->blending[1].alpha &&
 242                             state->blending[1].top)
 243                                 background[2] |= BLEND_CONTROL_ALPHA;
 244                         break;
 245                 }
 246         }
 247
 248         switch (state->base.normalized_zpos) {
 249         case 0:
 250                 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
 251                 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
 252                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 253                 break;
 254
 255         case 1:
 256                 /*
 257                  * If window B / C is topmost, then X / Y registers are
 258                  * matching the order of blending[...] state indices,
 259                  * otherwise a swap is required.
 260                  */
 261                 if (!state->blending[0].top && state->blending[1].top) {
 262                         blending[0] = foreground;
 263                         blending[1] = background[1];
 264                 } else {
 265                         blending[0] = background[0];
 266                         blending[1] = foreground;
 267                 }
 268
 269                 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
 270                 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
 271                 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
 272                 break;
 273
 274         case 2:
 275                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
 276                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
 277                 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
 278                 break;
 279         }
 280 }
 281
 282 static void tegra_plane_setup_blending(struct tegra_plane *plane,
 283                                        const struct tegra_dc_window *window)
 284 {
 285         u32 value;
 286
 287         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 288                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 289                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 290         tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
 291
 292         value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
 293                 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
 294                 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
 295         tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
 296
 297         value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
 298         tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
 299 }
 300
 301 static bool
 302 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
 303                                      const struct tegra_dc_window *window)
 304 {
 305         struct tegra_dc *dc = plane->dc;
 306
 307         if (window->src.w == window->dst.w)
 308                 return false;
 309
 310         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 311                 return false;
 312
 313         return true;
 314 }
 315
 316 static bool
 317 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
 318                                    const struct tegra_dc_window *window)
 319 {
 320         struct tegra_dc *dc = plane->dc;
 321
 322         if (window->src.h == window->dst.h)
 323                 return false;
 324
 325         if (plane->index == 0 && dc->soc->has_win_a_without_filters)
 326                 return false;
 327
 328         if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
 329                 return false;
 330
 331         return true;
 332 }
 333
 334 static void tegra_dc_setup_window(struct tegra_plane *plane,
 335                                   const struct tegra_dc_window *window)
 336 {
 337         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 338         struct tegra_dc *dc = plane->dc;
 339         bool yuv, planar;
 340         u32 value;
 341
 342         /*
 343          * For YUV planar modes, the number of bytes per pixel takes into
 344          * account only the luma component and therefore is 1.
 345          */
 346         yuv = tegra_plane_format_is_yuv(window->format, &planar);
 347         if (!yuv)
 348                 bpp = window->bits_per_pixel / 8;
 349         else
 350                 bpp = planar ? 1 : 2;
 351
 352         tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
 353         tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
 354
 355         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 356         tegra_plane_writel(plane, value, DC_WIN_POSITION);
 357
 358         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 359         tegra_plane_writel(plane, value, DC_WIN_SIZE);
 360
 361         h_offset = window->src.x * bpp;
 362         v_offset = window->src.y;
 363         h_size = window->src.w * bpp;
 364         v_size = window->src.h;
 365
 366         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 367         tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
 368
 369         /*
 370          * For DDA computations the number of bytes per pixel for YUV planar
 371          * modes needs to take into account all Y, U and V components.
 372          */
 373         if (yuv && planar)
 374                 bpp = 2;
 375
 376         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 377         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 378
 379         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 380         tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
 381
 382         h_dda = compute_initial_dda(window->src.x);
 383         v_dda = compute_initial_dda(window->src.y);
 384
 385         tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
 386         tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
 387
 388         tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
 389         tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
 390
 391         tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
 392
 393         if (yuv && planar) {
 394                 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
 395                 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
 396                 value = window->stride[1] << 16 | window->stride[0];
 397                 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
 398         } else {
 399                 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
 400         }
 401
 402         if (window->bottom_up)
 403                 v_offset += window->src.h - 1;
 404
 405         tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 406         tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 407
 408         if (dc->soc->supports_block_linear) {
 409                 unsigned long height = window->tiling.value;
 410
 411                 switch (window->tiling.mode) {
 412                 case TEGRA_BO_TILING_MODE_PITCH:
 413                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 414                         break;
 415
 416                 case TEGRA_BO_TILING_MODE_TILED:
 417                         value = DC_WINBUF_SURFACE_KIND_TILED;
 418                         break;
 419
 420                 case TEGRA_BO_TILING_MODE_BLOCK:
 421                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 422                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 423                         break;
 424                 }
 425
 426                 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
 427         } else {
 428                 switch (window->tiling.mode) {
 429                 case TEGRA_BO_TILING_MODE_PITCH:
 430                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 431                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 432                         break;
 433
 434                 case TEGRA_BO_TILING_MODE_TILED:
 435                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 436                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 437                         break;
 438
 439                 case TEGRA_BO_TILING_MODE_BLOCK:
 440                         /*
 441                          * No need to handle this here because ->atomic_check
 442                          * will already have filtered it out.
 443                          */
 444                         break;
 445                 }
 446
 447                 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
 448         }
 449
 450         value = WIN_ENABLE;
 451
 452         if (yuv) {
 453                 /* setup default colorspace conversion coefficients */
 454                 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
 455                 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
 456                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
 457                 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
 458                 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
 459                 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
 460                 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
 461                 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
 462
 463                 value |= CSC_ENABLE;
 464         } else if (window->bits_per_pixel < 24) {
 465                 value |= COLOR_EXPAND;
 466         }
 467
 468         if (window->bottom_up)
 469                 value |= V_DIRECTION;
 470
 471         if (tegra_plane_use_horizontal_filtering(plane, window)) {
 472                 /*
 473                  * Enable horizontal 6-tap filter and set filtering
 474                  * coefficients to the default values defined in TRM.
 475                  */
 476                 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
 477                 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
 478                 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
 479                 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
 480                 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
 481                 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
 482                 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
 483                 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
 484                 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
 485                 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
 486                 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
 487                 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
 488                 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
 489                 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
 490                 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
 491                 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
 492
 493                 value |= H_FILTER;
 494         }
 495
 496         if (tegra_plane_use_vertical_filtering(plane, window)) {
 497                 unsigned int i, k;
 498
 499                 /*
 500                  * Enable vertical 2-tap filter and set filtering
 501                  * coefficients to the default values defined in TRM.
 502                  */
 503                 for (i = 0, k = 128; i < 16; i++, k -= 8)
 504                         tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
 505
 506                 value |= V_FILTER;
 507         }
 508
 509         tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
 510
 511         if (dc->soc->has_legacy_blending)
 512                 tegra_plane_setup_blending_legacy(plane);
 513         else
 514                 tegra_plane_setup_blending(plane, window);
 515 }
 516
 517 static const u32 tegra20_primary_formats[] = {
 518         DRM_FORMAT_ARGB4444,
 519         DRM_FORMAT_ARGB1555,
 520         DRM_FORMAT_RGB565,
 521         DRM_FORMAT_RGBA5551,
 522         DRM_FORMAT_ABGR8888,
 523         DRM_FORMAT_ARGB8888,
 524         /* non-native formats */
 525         DRM_FORMAT_XRGB1555,
 526         DRM_FORMAT_RGBX5551,
 527         DRM_FORMAT_XBGR8888,
 528         DRM_FORMAT_XRGB8888,
 529 };
 530
 531 static const u64 tegra20_modifiers[] = {
 532         DRM_FORMAT_MOD_LINEAR,
 533         DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
 534         DRM_FORMAT_MOD_INVALID
 535 };
 536
 537 static const u32 tegra114_primary_formats[] = {
 538         DRM_FORMAT_ARGB4444,
 539         DRM_FORMAT_ARGB1555,
 540         DRM_FORMAT_RGB565,
 541         DRM_FORMAT_RGBA5551,
 542         DRM_FORMAT_ABGR8888,
 543         DRM_FORMAT_ARGB8888,
 544         /* new on Tegra114 */
 545         DRM_FORMAT_ABGR4444,
 546         DRM_FORMAT_ABGR1555,
 547         DRM_FORMAT_BGRA5551,
 548         DRM_FORMAT_XRGB1555,
 549         DRM_FORMAT_RGBX5551,
 550         DRM_FORMAT_XBGR1555,
 551         DRM_FORMAT_BGRX5551,
 552         DRM_FORMAT_BGR565,
 553         DRM_FORMAT_BGRA8888,
 554         DRM_FORMAT_RGBA8888,
 555         DRM_FORMAT_XRGB8888,
 556         DRM_FORMAT_XBGR8888,
 557 };
 558
 559 static const u32 tegra124_primary_formats[] = {
 560         DRM_FORMAT_ARGB4444,
 561         DRM_FORMAT_ARGB1555,
 562         DRM_FORMAT_RGB565,
 563         DRM_FORMAT_RGBA5551,
 564         DRM_FORMAT_ABGR8888,
 565         DRM_FORMAT_ARGB8888,
 566         /* new on Tegra114 */
 567         DRM_FORMAT_ABGR4444,
 568         DRM_FORMAT_ABGR1555,
 569         DRM_FORMAT_BGRA5551,
 570         DRM_FORMAT_XRGB1555,
 571         DRM_FORMAT_RGBX5551,
 572         DRM_FORMAT_XBGR1555,
 573         DRM_FORMAT_BGRX5551,
 574         DRM_FORMAT_BGR565,
 575         DRM_FORMAT_BGRA8888,
 576         DRM_FORMAT_RGBA8888,
 577         DRM_FORMAT_XRGB8888,
 578         DRM_FORMAT_XBGR8888,
 579         /* new on Tegra124 */
 580         DRM_FORMAT_RGBX8888,
 581         DRM_FORMAT_BGRX8888,
 582 };
 583
 584 static const u64 tegra124_modifiers[] = {
 585         DRM_FORMAT_MOD_LINEAR,
 586         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
 587         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
 588         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
 589         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
 590         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
 591         DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
 592         DRM_FORMAT_MOD_INVALID
 593 };
 594
 595 static int tegra_plane_atomic_check(struct drm_plane *plane,
 596                                     struct drm_plane_state *state)
 597 {
 598         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 599         unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
 600         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 601         struct tegra_plane *tegra = to_tegra_plane(plane);
 602         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 603         int err;
 604
 605         /* no need for further checks if the plane is being disabled */
 606         if (!state->crtc)
 607                 return 0;
 608
 609         err = tegra_plane_format(state->fb->format->format,
 610                                  &plane_state->format,
 611                                  &plane_state->swap);
 612         if (err < 0)
 613                 return err;
 614
 615         /*
 616          * Tegra20 and Tegra30 are special cases here because they support
 617          * only variants of specific formats with an alpha component, but not
 618          * the corresponding opaque formats. However, the opaque formats can
 619          * be emulated by disabling alpha blending for the plane.
 620          */
 621         if (dc->soc->has_legacy_blending) {
 622                 err = tegra_plane_setup_legacy_state(tegra, plane_state);
 623                 if (err < 0)
 624                         return err;
 625         }
 626
 627         err = tegra_fb_get_tiling(state->fb, tiling);
 628         if (err < 0)
 629                 return err;
 630
 631         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 632             !dc->soc->supports_block_linear) {
 633                 DRM_ERROR("hardware doesn't support block linear mode\n");
 634                 return -EINVAL;
 635         }
 636
 637         rotation = drm_rotation_simplify(state->rotation, rotation);
 638
 639         if (rotation & DRM_MODE_REFLECT_Y)
 640                 plane_state->bottom_up = true;
 641         else
 642                 plane_state->bottom_up = false;
 643
 644         /*
 645          * Tegra doesn't support different strides for U and V planes so we
 646          * error out if the user tries to display a framebuffer with such a
 647          * configuration.
 648          */
 649         if (state->fb->format->num_planes > 2) {
 650                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 651                         DRM_ERROR("unsupported UV-plane configuration\n");
 652                         return -EINVAL;
 653                 }
 654         }
 655
 656         err = tegra_plane_state_add(tegra, state);
 657         if (err < 0)
 658                 return err;
 659
 660         return 0;
 661 }
 662
 663 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 664                                        struct drm_plane_state *old_state)
 665 {
 666         struct tegra_plane *p = to_tegra_plane(plane);
 667         u32 value;
 668
 669         /* rien ne va plus */
 670         if (!old_state || !old_state->crtc)
 671                 return;
 672
 673         value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
 674         value &= ~WIN_ENABLE;
 675         tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
 676 }
 677
 678 static void tegra_plane_atomic_update(struct drm_plane *plane,
 679                                       struct drm_plane_state *old_state)
 680 {
 681         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 682         struct drm_framebuffer *fb = plane->state->fb;
 683         struct tegra_plane *p = to_tegra_plane(plane);
 684         struct tegra_dc_window window;
 685         unsigned int i;
 686
 687         /* rien ne va plus */
 688         if (!plane->state->crtc || !plane->state->fb)
 689                 return;
 690
 691         if (!plane->state->visible)
 692                 return tegra_plane_atomic_disable(plane, old_state);
 693
 694         memset(&window, 0, sizeof(window));
 695         window.src.x = plane->state->src.x1 >> 16;
 696         window.src.y = plane->state->src.y1 >> 16;
 697         window.src.w = drm_rect_width(&plane->state->src) >> 16;
 698         window.src.h = drm_rect_height(&plane->state->src) >> 16;
 699         window.dst.x = plane->state->dst.x1;
 700         window.dst.y = plane->state->dst.y1;
 701         window.dst.w = drm_rect_width(&plane->state->dst);
 702         window.dst.h = drm_rect_height(&plane->state->dst);
 703         window.bits_per_pixel = fb->format->cpp[0] * 8;
 704         window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
 705
 706         /* copy from state */
 707         window.zpos = plane->state->normalized_zpos;
 708         window.tiling = state->tiling;
 709         window.format = state->format;
 710         window.swap = state->swap;
 711
 712         for (i = 0; i < fb->format->num_planes; i++) {
 713                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 714
 715                 window.base[i] = bo->paddr + fb->offsets[i];
 716
 717                 /*
 718                  * Tegra uses a shared stride for UV planes. Framebuffers are
 719                  * already checked for this in the tegra_plane_atomic_check()
 720                  * function, so it's safe to ignore the V-plane pitch here.
 721                  */
 722                 if (i < 2)
 723                         window.stride[i] = fb->pitches[i];
 724         }
 725
 726         tegra_dc_setup_window(p, &window);
 727 }
 728
 729 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 730         .atomic_check = tegra_plane_atomic_check,
 731         .atomic_disable = tegra_plane_atomic_disable,
 732         .atomic_update = tegra_plane_atomic_update,
 733 };
 734
 735 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
 736 {
 737         /*
 738          * Ideally this would use drm_crtc_mask(), but that would require the
 739          * CRTC to already be in the mode_config's list of CRTCs. However, it
 740          * will only be added to that list in the drm_crtc_init_with_planes()
 741          * (in tegra_dc_init()), which in turn requires registration of these
 742          * planes. So we have ourselves a nice little chicken and egg problem
 743          * here.
 744          *
 745          * We work around this by manually creating the mask from the number
 746          * of CRTCs that have been registered, and should therefore always be
 747          * the same as drm_crtc_index() after registration.
 748          */
 749         return 1 << drm->mode_config.num_crtc;
 750 }
 751
 752 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
 753                                                     struct tegra_dc *dc)
 754 {
 755         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 756         enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
 757         struct tegra_plane *plane;
 758         unsigned int num_formats;
 759         const u64 *modifiers;
 760         const u32 *formats;
 761         int err;
 762
 763         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 764         if (!plane)
 765                 return ERR_PTR(-ENOMEM);
 766
 767         /* Always use window A as primary window */
 768         plane->offset = 0xa00;
 769         plane->index = 0;
 770         plane->dc = dc;
 771
 772         num_formats = dc->soc->num_primary_formats;
 773         formats = dc->soc->primary_formats;
 774         modifiers = dc->soc->modifiers;
 775
 776         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 777                                        &tegra_plane_funcs, formats,
 778                                        num_formats, modifiers, type, NULL);
 779         if (err < 0) {
 780                 kfree(plane);
 781                 return ERR_PTR(err);
 782         }
 783
 784         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 785         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
 786
 787         err = drm_plane_create_rotation_property(&plane->base,
 788                                                  DRM_MODE_ROTATE_0,
 789                                                  DRM_MODE_ROTATE_0 |
 790                                                  DRM_MODE_REFLECT_Y);
 791         if (err < 0)
 792                 dev_err(dc->dev, "failed to create rotation property: %d\n",
 793                         err);
 794
 795         return &plane->base;
 796 }
 797
 798 static const u32 tegra_cursor_plane_formats[] = {
 799         DRM_FORMAT_RGBA8888,
 800 };
 801
 802 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 803                                      struct drm_plane_state *state)
 804 {
 805         struct tegra_plane *tegra = to_tegra_plane(plane);
 806         int err;
 807
 808         /* no need for further checks if the plane is being disabled */
 809         if (!state->crtc)
 810                 return 0;
 811
 812         /* scaling not supported for cursor */
 813         if ((state->src_w >> 16 != state->crtc_w) ||
 814             (state->src_h >> 16 != state->crtc_h))
 815                 return -EINVAL;
 816
 817         /* only square cursors supported */
 818         if (state->src_w != state->src_h)
 819                 return -EINVAL;
 820
 821         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 822             state->crtc_w != 128 && state->crtc_w != 256)
 823                 return -EINVAL;
 824
 825         err = tegra_plane_state_add(tegra, state);
 826         if (err < 0)
 827                 return err;
 828
 829         return 0;
 830 }
 831
 832 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 833                                        struct drm_plane_state *old_state)
 834 {
 835         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 836         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 837         struct drm_plane_state *state = plane->state;
 838         u32 value = CURSOR_CLIP_DISPLAY;
 839
 840         /* rien ne va plus */
 841         if (!plane->state->crtc || !plane->state->fb)
 842                 return;
 843
 844         switch (state->crtc_w) {
 845         case 32:
 846                 value |= CURSOR_SIZE_32x32;
 847                 break;
 848
 849         case 64:
 850                 value |= CURSOR_SIZE_64x64;
 851                 break;
 852
 853         case 128:
 854                 value |= CURSOR_SIZE_128x128;
 855                 break;
 856
 857         case 256:
 858                 value |= CURSOR_SIZE_256x256;
 859                 break;
 860
 861         default:
 862                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 863                      state->crtc_h);
 864                 return;
 865         }
 866
 867         value |= (bo->paddr >> 10) & 0x3fffff;
 868         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 869
 870 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 871         value = (bo->paddr >> 32) & 0x3;
 872         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 873 #endif
 874
 875         /* enable cursor and set blend mode */
 876         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 877         value |= CURSOR_ENABLE;
 878         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 879
 880         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 881         value &= ~CURSOR_DST_BLEND_MASK;
 882         value &= ~CURSOR_SRC_BLEND_MASK;
 883         value |= CURSOR_MODE_NORMAL;
 884         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 885         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 886         value |= CURSOR_ALPHA;
 887         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 888
 889         /* position the cursor */
 890         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 891         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 892 }
 893
 894 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 895                                         struct drm_plane_state *old_state)
 896 {
 897         struct tegra_dc *dc;
 898         u32 value;
 899
 900         /* rien ne va plus */
 901         if (!old_state || !old_state->crtc)
 902                 return;
 903
 904         dc = to_tegra_dc(old_state->crtc);
 905
 906         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 907         value &= ~CURSOR_ENABLE;
 908         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 909 }
 910
 911 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 912         .atomic_check = tegra_cursor_atomic_check,
 913         .atomic_update = tegra_cursor_atomic_update,
 914         .atomic_disable = tegra_cursor_atomic_disable,
 915 };
 916
 917 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 918                                                       struct tegra_dc *dc)
 919 {
 920         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
 921         struct tegra_plane *plane;
 922         unsigned int num_formats;
 923         const u32 *formats;
 924         int err;
 925
 926         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 927         if (!plane)
 928                 return ERR_PTR(-ENOMEM);
 929
 930         /*
 931          * This index is kind of fake. The cursor isn't a regular plane, but
 932          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 933          * use the same programming. Setting this fake index here allows the
 934          * code in tegra_add_plane_state() to do the right thing without the
 935          * need to special-casing the cursor plane.
 936          */
 937         plane->index = 6;
 938         plane->dc = dc;
 939
 940         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 941         formats = tegra_cursor_plane_formats;
 942
 943         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 944                                        &tegra_plane_funcs, formats,
 945                                        num_formats, NULL,
 946                                        DRM_PLANE_TYPE_CURSOR, NULL);
 947         if (err < 0) {
 948                 kfree(plane);
 949                 return ERR_PTR(err);
 950         }
 951
 952         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 953
 954         return &plane->base;
 955 }
 956
 957 static const u32 tegra20_overlay_formats[] = {
 958         DRM_FORMAT_ARGB4444,
 959         DRM_FORMAT_ARGB1555,
 960         DRM_FORMAT_RGB565,
 961         DRM_FORMAT_RGBA5551,
 962         DRM_FORMAT_ABGR8888,
 963         DRM_FORMAT_ARGB8888,
 964         /* non-native formats */
 965         DRM_FORMAT_XRGB1555,
 966         DRM_FORMAT_RGBX5551,
 967         DRM_FORMAT_XBGR8888,
 968         DRM_FORMAT_XRGB8888,
 969         /* planar formats */
 970         DRM_FORMAT_UYVY,
 971         DRM_FORMAT_YUYV,
 972         DRM_FORMAT_YUV420,
 973         DRM_FORMAT_YUV422,
 974 };
 975
 976 static const u32 tegra114_overlay_formats[] = {
 977         DRM_FORMAT_ARGB4444,
 978         DRM_FORMAT_ARGB1555,
 979         DRM_FORMAT_RGB565,
 980         DRM_FORMAT_RGBA5551,
 981         DRM_FORMAT_ABGR8888,
 982         DRM_FORMAT_ARGB8888,
 983         /* new on Tegra114 */
 984         DRM_FORMAT_ABGR4444,
 985         DRM_FORMAT_ABGR1555,
 986         DRM_FORMAT_BGRA5551,
 987         DRM_FORMAT_XRGB1555,
 988         DRM_FORMAT_RGBX5551,
 989         DRM_FORMAT_XBGR1555,
 990         DRM_FORMAT_BGRX5551,
 991         DRM_FORMAT_BGR565,
 992         DRM_FORMAT_BGRA8888,
 993         DRM_FORMAT_RGBA8888,
 994         DRM_FORMAT_XRGB8888,
 995         DRM_FORMAT_XBGR8888,
 996         /* planar formats */
 997         DRM_FORMAT_UYVY,
 998         DRM_FORMAT_YUYV,
 999         DRM_FORMAT_YUV420,
1000         DRM_FORMAT_YUV422,
1001 };
1002
1003 static const u32 tegra124_overlay_formats[] = {
1004         DRM_FORMAT_ARGB4444,
1005         DRM_FORMAT_ARGB1555,
1006         DRM_FORMAT_RGB565,
1007         DRM_FORMAT_RGBA5551,
1008         DRM_FORMAT_ABGR8888,
1009         DRM_FORMAT_ARGB8888,
1010         /* new on Tegra114 */
1011         DRM_FORMAT_ABGR4444,
1012         DRM_FORMAT_ABGR1555,
1013         DRM_FORMAT_BGRA5551,
1014         DRM_FORMAT_XRGB1555,
1015         DRM_FORMAT_RGBX5551,
1016         DRM_FORMAT_XBGR1555,
1017         DRM_FORMAT_BGRX5551,
1018         DRM_FORMAT_BGR565,
1019         DRM_FORMAT_BGRA8888,
1020         DRM_FORMAT_RGBA8888,
1021         DRM_FORMAT_XRGB8888,
1022         DRM_FORMAT_XBGR8888,
1023         /* new on Tegra124 */
1024         DRM_FORMAT_RGBX8888,
1025         DRM_FORMAT_BGRX8888,
1026         /* planar formats */
1027         DRM_FORMAT_UYVY,
1028         DRM_FORMAT_YUYV,
1029         DRM_FORMAT_YUV420,
1030         DRM_FORMAT_YUV422,
1031 };
1032
1033 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1034                                                        struct tegra_dc *dc,
1035                                                        unsigned int index,
1036                                                        bool cursor)
1037 {
1038         unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1039         struct tegra_plane *plane;
1040         unsigned int num_formats;
1041         enum drm_plane_type type;
1042         const u32 *formats;
1043         int err;
1044
1045         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1046         if (!plane)
1047                 return ERR_PTR(-ENOMEM);
1048
1049         plane->offset = 0xa00 + 0x200 * index;
1050         plane->index = index;
1051         plane->dc = dc;
1052
1053         num_formats = dc->soc->num_overlay_formats;
1054         formats = dc->soc->overlay_formats;
1055
1056         if (!cursor)
1057                 type = DRM_PLANE_TYPE_OVERLAY;
1058         else
1059                 type = DRM_PLANE_TYPE_CURSOR;
1060
1061         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1062                                        &tegra_plane_funcs, formats,
1063                                        num_formats, NULL, type, NULL);
1064         if (err < 0) {
1065                 kfree(plane);
1066                 return ERR_PTR(err);
1067         }
1068
1069         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1070         drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1071
1072         err = drm_plane_create_rotation_property(&plane->base,
1073                                                  DRM_MODE_ROTATE_0,
1074                                                  DRM_MODE_ROTATE_0 |
1075                                                  DRM_MODE_REFLECT_Y);
1076         if (err < 0)
1077                 dev_err(dc->dev, "failed to create rotation property: %d\n",
1078                         err);
1079
1080         return &plane->base;
1081 }
1082
1083 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1084                                                     struct tegra_dc *dc)
1085 {
1086         struct drm_plane *plane, *primary = NULL;
1087         unsigned int i, j;
1088
1089         for (i = 0; i < dc->soc->num_wgrps; i++) {
1090                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1091
1092                 if (wgrp->dc == dc->pipe) {
1093                         for (j = 0; j < wgrp->num_windows; j++) {
1094                                 unsigned int index = wgrp->windows[j];
1095
1096                                 plane = tegra_shared_plane_create(drm, dc,
1097                                                                   wgrp->index,
1098                                                                   index);
1099                                 if (IS_ERR(plane))
1100                                         return plane;
1101
1102                                 /*
1103                                  * Choose the first shared plane owned by this
1104                                  * head as the primary plane.
1105                                  */
1106                                 if (!primary) {
1107                                         plane->type = DRM_PLANE_TYPE_PRIMARY;
1108                                         primary = plane;
1109                                 }
1110                         }
1111                 }
1112         }
1113
1114         return primary;
1115 }
1116
1117 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1118                                              struct tegra_dc *dc)
1119 {
1120         struct drm_plane *planes[2], *primary;
1121         unsigned int planes_num;
1122         unsigned int i;
1123         int err;
1124
1125         primary = tegra_primary_plane_create(drm, dc);
1126         if (IS_ERR(primary))
1127                 return primary;
1128
1129         if (dc->soc->supports_cursor)
1130                 planes_num = 2;
1131         else
1132                 planes_num = 1;
1133
1134         for (i = 0; i < planes_num; i++) {
1135                 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1136                                                           false);
1137                 if (IS_ERR(planes[i])) {
1138                         err = PTR_ERR(planes[i]);
1139
1140                         while (i--)
1141                                 tegra_plane_funcs.destroy(planes[i]);
1142
1143                         tegra_plane_funcs.destroy(primary);
1144                         return ERR_PTR(err);
1145                 }
1146         }
1147
1148         return primary;
1149 }
1150
1151 static void tegra_dc_destroy(struct drm_crtc *crtc)
1152 {
1153         drm_crtc_cleanup(crtc);
1154 }
1155
1156 static void tegra_crtc_reset(struct drm_crtc *crtc)
1157 {
1158         struct tegra_dc_state *state;
1159
1160         if (crtc->state)
1161                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1162
1163         kfree(crtc->state);
1164         crtc->state = NULL;
1165
1166         state = kzalloc(sizeof(*state), GFP_KERNEL);
1167         if (state) {
1168                 crtc->state = &state->base;
1169                 crtc->state->crtc = crtc;
1170         }
1171
1172         drm_crtc_vblank_reset(crtc);
1173 }
1174
1175 static struct drm_crtc_state *
1176 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1177 {
1178         struct tegra_dc_state *state = to_dc_state(crtc->state);
1179         struct tegra_dc_state *copy;
1180
1181         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1182         if (!copy)
1183                 return NULL;
1184
1185         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1186         copy->clk = state->clk;
1187         copy->pclk = state->pclk;
1188         copy->div = state->div;
1189         copy->planes = state->planes;
1190
1191         return &copy->base;
1192 }
1193
1194 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1195                                             struct drm_crtc_state *state)
1196 {
1197         __drm_atomic_helper_crtc_destroy_state(state);
1198         kfree(state);
1199 }
1200
1201 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1202
1203 static const struct debugfs_reg32 tegra_dc_regs[] = {
1204         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1205         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1206         DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1207         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1208         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1209         DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1210         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1211         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1212         DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1213         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1214         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1215         DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1216         DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1217         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1218         DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1219         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1220         DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1221         DEBUGFS_REG32(DC_CMD_INT_STATUS),
1222         DEBUGFS_REG32(DC_CMD_INT_MASK),
1223         DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1224         DEBUGFS_REG32(DC_CMD_INT_TYPE),
1225         DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1226         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1227         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1228         DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1229         DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1230         DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1231         DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1232         DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1233         DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1234         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1235         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1236         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1237         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1238         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1239         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1240         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1241         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1242         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1243         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1244         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1245         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1246         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1247         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1248         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1249         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1250         DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1251         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1252         DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1253         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1254         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1255         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1256         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1257         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1258         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1259         DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1260         DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1261         DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1262         DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1263         DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1264         DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1265         DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1266         DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1267         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1268         DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1269         DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1270         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1271         DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1272         DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1273         DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1274         DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1275         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1276         DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1277         DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1278         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1279         DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1280         DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1281         DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1282         DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1283         DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1284         DEBUGFS_REG32(DC_DISP_ACTIVE),
1285         DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1286         DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1287         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1288         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1289         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1290         DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1291         DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1292         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1293         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1294         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1295         DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1296         DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1297         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1298         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1299         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1300         DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1301         DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1302         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1303         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1304         DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1305         DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1306         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1307         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1308         DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1309         DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1310         DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1311         DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1312         DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1313         DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1314         DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1315         DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1316         DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1317         DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1318         DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1319         DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1320         DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1321         DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1322         DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1323         DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1324         DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1325         DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1326         DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1327         DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1328         DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1329         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1330         DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1331         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1332         DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1333         DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1334         DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1335         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1336         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1337         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1338         DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1339         DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1340         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1341         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1342         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1343         DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1344         DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1345         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1346         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1347         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1348         DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1349         DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1350         DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1351         DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1352         DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1353         DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1354         DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1355         DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1356         DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1357         DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1358         DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1359         DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1360         DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1361         DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1362         DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1363         DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1364         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1365         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1366         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1367         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1368         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1369         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1370         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1371         DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1372         DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1373         DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1374         DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1375         DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1376         DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1377         DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1378         DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1379         DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1380         DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1381         DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1382         DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1383         DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1384         DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1385         DEBUGFS_REG32(DC_WIN_POSITION),
1386         DEBUGFS_REG32(DC_WIN_SIZE),
1387         DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1388         DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1389         DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1390         DEBUGFS_REG32(DC_WIN_DDA_INC),
1391         DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1392         DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1393         DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1394         DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1395         DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1396         DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1397         DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1398         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1399         DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1400         DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1401         DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1402         DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1403         DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1404         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1405         DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1406         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1407         DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1408         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1409         DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1410         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1411         DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1412         DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1413         DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1414         DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1415         DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1416 };
1417
1418 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1419 {
1420         struct drm_info_node *node = s->private;
1421         struct tegra_dc *dc = node->info_ent->data;
1422         unsigned int i;
1423         int err = 0;
1424
1425         drm_modeset_lock(&dc->base.mutex, NULL);
1426
1427         if (!dc->base.state->active) {
1428                 err = -EBUSY;
1429                 goto unlock;
1430         }
1431
1432         for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1433                 unsigned int offset = tegra_dc_regs[i].offset;
1434
1435                 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1436                            offset, tegra_dc_readl(dc, offset));
1437         }
1438
1439 unlock:
1440         drm_modeset_unlock(&dc->base.mutex);
1441         return err;
1442 }
1443
1444 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1445 {
1446         struct drm_info_node *node = s->private;
1447         struct tegra_dc *dc = node->info_ent->data;
1448         int err = 0;
1449         u32 value;
1450
1451         drm_modeset_lock(&dc->base.mutex, NULL);
1452
1453         if (!dc->base.state->active) {
1454                 err = -EBUSY;
1455                 goto unlock;
1456         }
1457
1458         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1459         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1460         tegra_dc_commit(dc);
1461
1462         drm_crtc_wait_one_vblank(&dc->base);
1463         drm_crtc_wait_one_vblank(&dc->base);
1464
1465         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1466         seq_printf(s, "%08x\n", value);
1467
1468         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1469
1470 unlock:
1471         drm_modeset_unlock(&dc->base.mutex);
1472         return err;
1473 }
1474
1475 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1476 {
1477         struct drm_info_node *node = s->private;
1478         struct tegra_dc *dc = node->info_ent->data;
1479
1480         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1481         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1482         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1483         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1484
1485         return 0;
1486 }
1487
1488 static struct drm_info_list debugfs_files[] = {
1489         { "regs", tegra_dc_show_regs, 0, NULL },
1490         { "crc", tegra_dc_show_crc, 0, NULL },
1491         { "stats", tegra_dc_show_stats, 0, NULL },
1492 };
1493
1494 static int tegra_dc_late_register(struct drm_crtc *crtc)
1495 {
1496         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1497         struct drm_minor *minor = crtc->dev->primary;
1498         struct dentry *root;
1499         struct tegra_dc *dc = to_tegra_dc(crtc);
1500         int err;
1501
1502 #ifdef CONFIG_DEBUG_FS
1503         root = crtc->debugfs_entry;
1504 #else
1505         root = NULL;
1506 #endif
1507
1508         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1509                                     GFP_KERNEL);
1510         if (!dc->debugfs_files)
1511                 return -ENOMEM;
1512
1513         for (i = 0; i < count; i++)
1514                 dc->debugfs_files[i].data = dc;
1515
1516         err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1517         if (err < 0)
1518                 goto free;
1519
1520         return 0;
1521
1522 free:
1523         kfree(dc->debugfs_files);
1524         dc->debugfs_files = NULL;
1525
1526         return err;
1527 }
1528
1529 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1530 {
1531         unsigned int count = ARRAY_SIZE(debugfs_files);
1532         struct drm_minor *minor = crtc->dev->primary;
1533         struct tegra_dc *dc = to_tegra_dc(crtc);
1534
1535         drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1536         kfree(dc->debugfs_files);
1537         dc->debugfs_files = NULL;
1538 }
1539
1540 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1541 {
1542         struct tegra_dc *dc = to_tegra_dc(crtc);
1543
1544         /* XXX vblank syncpoints don't work with nvdisplay yet */
1545         if (dc->syncpt && !dc->soc->has_nvdisplay)
1546                 return host1x_syncpt_read(dc->syncpt);
1547
1548         /* fallback to software emulated VBLANK counter */
1549         return (u32)drm_crtc_vblank_count(&dc->base);
1550 }
1551
1552 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1553 {
1554         struct tegra_dc *dc = to_tegra_dc(crtc);
1555         u32 value;
1556
1557         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1558         value |= VBLANK_INT;
1559         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1560
1561         return 0;
1562 }
1563
1564 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1565 {
1566         struct tegra_dc *dc = to_tegra_dc(crtc);
1567         u32 value;
1568
1569         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1570         value &= ~VBLANK_INT;
1571         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1572 }
1573
1574 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1575         .page_flip = drm_atomic_helper_page_flip,
1576         .set_config = drm_atomic_helper_set_config,
1577         .destroy = tegra_dc_destroy,
1578         .reset = tegra_crtc_reset,
1579         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1580         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1581         .late_register = tegra_dc_late_register,
1582         .early_unregister = tegra_dc_early_unregister,
1583         .get_vblank_counter = tegra_dc_get_vblank_counter,
1584         .enable_vblank = tegra_dc_enable_vblank,
1585         .disable_vblank = tegra_dc_disable_vblank,
1586 };
1587
1588 static int tegra_dc_set_timings(struct tegra_dc *dc,
1589                                 struct drm_display_mode *mode)
1590 {
1591         unsigned int h_ref_to_sync = 1;
1592         unsigned int v_ref_to_sync = 1;
1593         unsigned long value;
1594
1595         if (!dc->soc->has_nvdisplay) {
1596                 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1597
1598                 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1599                 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1600         }
1601
1602         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1603                 ((mode->hsync_end - mode->hsync_start) <<  0);
1604         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1605
1606         value = ((mode->vtotal - mode->vsync_end) << 16) |
1607                 ((mode->htotal - mode->hsync_end) <<  0);
1608         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1609
1610         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1611                 ((mode->hsync_start - mode->hdisplay) <<  0);
1612         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1613
1614         value = (mode->vdisplay << 16) | mode->hdisplay;
1615         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1616
1617         return 0;
1618 }
1619
1620 /**
1621  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1622  *     state
1623  * @dc: display controller
1624  * @crtc_state: CRTC atomic state
1625  * @clk: parent clock for display controller
1626  * @pclk: pixel clock
1627  * @div: shift clock divider
1628  *
1629  * Returns:
1630  * 0 on success or a negative error-code on failure.
1631  */
1632 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1633                                struct drm_crtc_state *crtc_state,
1634                                struct clk *clk, unsigned long pclk,
1635                                unsigned int div)
1636 {
1637         struct tegra_dc_state *state = to_dc_state(crtc_state);
1638
1639         if (!clk_has_parent(dc->clk, clk))
1640                 return -EINVAL;
1641
1642         state->clk = clk;
1643         state->pclk = pclk;
1644         state->div = div;
1645
1646         return 0;
1647 }
1648
1649 static void tegra_dc_commit_state(struct tegra_dc *dc,
1650                                   struct tegra_dc_state *state)
1651 {
1652         u32 value;
1653         int err;
1654
1655         err = clk_set_parent(dc->clk, state->clk);
1656         if (err < 0)
1657                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1658
1659         /*
1660          * Outputs may not want to change the parent clock rate. This is only
1661          * relevant to Tegra20 where only a single display PLL is available.
1662          * Since that PLL would typically be used for HDMI, an internal LVDS
1663          * panel would need to be driven by some other clock such as PLL_P
1664          * which is shared with other peripherals. Changing the clock rate
1665          * should therefore be avoided.
1666          */
1667         if (state->pclk > 0) {
1668                 err = clk_set_rate(state->clk, state->pclk);
1669                 if (err < 0)
1670                         dev_err(dc->dev,
1671                                 "failed to set clock rate to %lu Hz\n",
1672                                 state->pclk);
1673         }
1674
1675         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1676                       state->div);
1677         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1678
1679         if (!dc->soc->has_nvdisplay) {
1680                 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1681                 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1682         }
1683
1684         err = clk_set_rate(dc->clk, state->pclk);
1685         if (err < 0)
1686                 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1687                         dc->clk, state->pclk, err);
1688 }
1689
1690 static void tegra_dc_stop(struct tegra_dc *dc)
1691 {
1692         u32 value;
1693
1694         /* stop the display controller */
1695         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1696         value &= ~DISP_CTRL_MODE_MASK;
1697         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1698
1699         tegra_dc_commit(dc);
1700 }
1701
1702 static bool tegra_dc_idle(struct tegra_dc *dc)
1703 {
1704         u32 value;
1705
1706         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1707
1708         return (value & DISP_CTRL_MODE_MASK) == 0;
1709 }
1710
1711 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1712 {
1713         timeout = jiffies + msecs_to_jiffies(timeout);
1714
1715         while (time_before(jiffies, timeout)) {
1716                 if (tegra_dc_idle(dc))
1717                         return 0;
1718
1719                 usleep_range(1000, 2000);
1720         }
1721
1722         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1723         return -ETIMEDOUT;
1724 }
1725
1726 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1727                                       struct drm_crtc_state *old_state)
1728 {
1729         struct tegra_dc *dc = to_tegra_dc(crtc);
1730         u32 value;
1731
1732         if (!tegra_dc_idle(dc)) {
1733                 tegra_dc_stop(dc);
1734
1735                 /*
1736                  * Ignore the return value, there isn't anything useful to do
1737                  * in case this fails.
1738                  */
1739                 tegra_dc_wait_idle(dc, 100);
1740         }
1741
1742         /*
1743          * This should really be part of the RGB encoder driver, but clearing
1744          * these bits has the side-effect of stopping the display controller.
1745          * When that happens no VBLANK interrupts will be raised. At the same
1746          * time the encoder is disabled before the display controller, so the
1747          * above code is always going to timeout waiting for the controller
1748          * to go idle.
1749          *
1750          * Given the close coupling between the RGB encoder and the display
1751          * controller doing it here is still kind of okay. None of the other
1752          * encoder drivers require these bits to be cleared.
1753          *
1754          * XXX: Perhaps given that the display controller is switched off at
1755          * this point anyway maybe clearing these bits isn't even useful for
1756          * the RGB encoder?
1757          */
1758         if (dc->rgb) {
1759                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1760                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1761                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1762                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1763         }
1764
1765         tegra_dc_stats_reset(&dc->stats);
1766         drm_crtc_vblank_off(crtc);
1767
1768         spin_lock_irq(&crtc->dev->event_lock);
1769
1770         if (crtc->state->event) {
1771                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1772                 crtc->state->event = NULL;
1773         }
1774
1775         spin_unlock_irq(&crtc->dev->event_lock);
1776
1777         pm_runtime_put_sync(dc->dev);
1778 }
1779
1780 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1781                                      struct drm_crtc_state *old_state)
1782 {
1783         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1784         struct tegra_dc_state *state = to_dc_state(crtc->state);
1785         struct tegra_dc *dc = to_tegra_dc(crtc);
1786         u32 value;
1787
1788         pm_runtime_get_sync(dc->dev);
1789
1790         /* initialize display controller */
1791         if (dc->syncpt) {
1792                 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1793
1794                 if (dc->soc->has_nvdisplay)
1795                         enable = 1 << 31;
1796                 else
1797                         enable = 1 << 8;
1798
1799                 value = SYNCPT_CNTRL_NO_STALL;
1800                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1801
1802                 value = enable | syncpt;
1803                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1804         }
1805
1806         if (dc->soc->has_nvdisplay) {
1807                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1808                         DSC_OBUF_UF_INT;
1809                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1810
1811                 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1812                         DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1813                         HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1814                         REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1815                         VBLANK_INT | FRAME_END_INT;
1816                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1817
1818                 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1819                         FRAME_END_INT;
1820                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1821
1822                 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1823                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1824
1825                 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1826         } else {
1827                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1828                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1829                 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1830
1831                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1832                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1833                 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1834
1835                 /* initialize timer */
1836                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1837                         WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1838                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1839
1840                 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1841                         WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1842                 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1843
1844                 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1845                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1846                 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1847
1848                 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1849                         WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1850                 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1851         }
1852
1853         if (dc->soc->supports_background_color)
1854                 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1855         else
1856                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1857
1858         /* apply PLL and pixel clock changes */
1859         tegra_dc_commit_state(dc, state);
1860
1861         /* program display mode */
1862         tegra_dc_set_timings(dc, mode);
1863
1864         /* interlacing isn't supported yet, so disable it */
1865         if (dc->soc->supports_interlacing) {
1866                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1867                 value &= ~INTERLACE_ENABLE;
1868                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1869         }
1870
1871         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1872         value &= ~DISP_CTRL_MODE_MASK;
1873         value |= DISP_CTRL_MODE_C_DISPLAY;
1874         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1875
1876         if (!dc->soc->has_nvdisplay) {
1877                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1878                 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1879                          PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1880                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1881         }
1882
1883         /* enable underflow reporting and display red for missing pixels */
1884         if (dc->soc->has_nvdisplay) {
1885                 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1886                 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1887         }
1888
1889         tegra_dc_commit(dc);
1890
1891         drm_crtc_vblank_on(crtc);
1892 }
1893
1894 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1895                                     struct drm_crtc_state *old_crtc_state)
1896 {
1897         unsigned long flags;
1898
1899         if (crtc->state->event) {
1900                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1901
1902                 if (drm_crtc_vblank_get(crtc) != 0)
1903                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
1904                 else
1905                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1906
1907                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1908
1909                 crtc->state->event = NULL;
1910         }
1911 }
1912
1913 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1914                                     struct drm_crtc_state *old_crtc_state)
1915 {
1916         struct tegra_dc_state *state = to_dc_state(crtc->state);
1917         struct tegra_dc *dc = to_tegra_dc(crtc);
1918         u32 value;
1919
1920         value = state->planes << 8 | GENERAL_UPDATE;
1921         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1922         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1923
1924         value = state->planes | GENERAL_ACT_REQ;
1925         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1926         value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1927 }
1928
1929 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1930         .atomic_begin = tegra_crtc_atomic_begin,
1931         .atomic_flush = tegra_crtc_atomic_flush,
1932         .atomic_enable = tegra_crtc_atomic_enable,
1933         .atomic_disable = tegra_crtc_atomic_disable,
1934 };
1935
1936 static irqreturn_t tegra_dc_irq(int irq, void *data)
1937 {
1938         struct tegra_dc *dc = data;
1939         unsigned long status;
1940
1941         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1942         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1943
1944         if (status & FRAME_END_INT) {
1945                 /*
1946                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1947                 */
1948                 dc->stats.frames++;
1949         }
1950
1951         if (status & VBLANK_INT) {
1952                 /*
1953                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1954                 */
1955                 drm_crtc_handle_vblank(&dc->base);
1956                 dc->stats.vblank++;
1957         }
1958
1959         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1960                 /*
1961                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1962                 */
1963                 dc->stats.underflow++;
1964         }
1965
1966         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1967                 /*
1968                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1969                 */
1970                 dc->stats.overflow++;
1971         }
1972
1973         if (status & HEAD_UF_INT) {
1974                 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1975                 dc->stats.underflow++;
1976         }
1977
1978         return IRQ_HANDLED;
1979 }
1980
1981 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1982 {
1983         unsigned int i;
1984
1985         if (!dc->soc->wgrps)
1986                 return true;
1987
1988         for (i = 0; i < dc->soc->num_wgrps; i++) {
1989                 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1990
1991                 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1992                         return true;
1993         }
1994
1995         return false;
1996 }
1997
1998 static int tegra_dc_init(struct host1x_client *client)
1999 {
2000         struct drm_device *drm = dev_get_drvdata(client->parent);
2001         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2002         struct tegra_dc *dc = host1x_client_to_dc(client);
2003         struct tegra_drm *tegra = drm->dev_private;
2004         struct drm_plane *primary = NULL;
2005         struct drm_plane *cursor = NULL;
2006         int err;
2007
2008         /*
2009          * XXX do not register DCs with no window groups because we cannot
2010          * assign a primary plane to them, which in turn will cause KMS to
2011          * crash.
2012          */
2013         if (!tegra_dc_has_window_groups(dc))
2014                 return 0;
2015
2016         dc->syncpt = host1x_syncpt_request(client, flags);
2017         if (!dc->syncpt)
2018                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2019
2020         dc->group = host1x_client_iommu_attach(client, true);
2021         if (IS_ERR(dc->group)) {
2022                 err = PTR_ERR(dc->group);
2023                 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2024                 return err;
2025         }
2026
2027         if (dc->soc->wgrps)
2028                 primary = tegra_dc_add_shared_planes(drm, dc);
2029         else
2030                 primary = tegra_dc_add_planes(drm, dc);
2031
2032         if (IS_ERR(primary)) {
2033                 err = PTR_ERR(primary);
2034                 goto cleanup;
2035         }
2036
2037         if (dc->soc->supports_cursor) {
2038                 cursor = tegra_dc_cursor_plane_create(drm, dc);
2039                 if (IS_ERR(cursor)) {
2040                         err = PTR_ERR(cursor);
2041                         goto cleanup;
2042                 }
2043         } else {
2044                 /* dedicate one overlay to mouse cursor */
2045                 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2046                 if (IS_ERR(cursor)) {
2047                         err = PTR_ERR(cursor);
2048                         goto cleanup;
2049                 }
2050         }
2051
2052         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2053                                         &tegra_crtc_funcs, NULL);
2054         if (err < 0)
2055                 goto cleanup;
2056
2057         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2058
2059         /*
2060          * Keep track of the minimum pitch alignment across all display
2061          * controllers.
2062          */
2063         if (dc->soc->pitch_align > tegra->pitch_align)
2064                 tegra->pitch_align = dc->soc->pitch_align;
2065
2066         err = tegra_dc_rgb_init(drm, dc);
2067         if (err < 0 && err != -ENODEV) {
2068                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2069                 goto cleanup;
2070         }
2071
2072         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2073                                dev_name(dc->dev), dc);
2074         if (err < 0) {
2075                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2076                         err);
2077                 goto cleanup;
2078         }
2079
2080         return 0;
2081
2082 cleanup:
2083         if (!IS_ERR_OR_NULL(cursor))
2084                 drm_plane_cleanup(cursor);
2085
2086         if (!IS_ERR(primary))
2087                 drm_plane_cleanup(primary);
2088
2089         host1x_client_iommu_detach(client, dc->group);
2090         host1x_syncpt_free(dc->syncpt);
2091
2092         return err;
2093 }
2094
2095 static int tegra_dc_exit(struct host1x_client *client)
2096 {
2097         struct tegra_dc *dc = host1x_client_to_dc(client);
2098         int err;
2099
2100         if (!tegra_dc_has_window_groups(dc))
2101                 return 0;
2102
2103         devm_free_irq(dc->dev, dc->irq, dc);
2104
2105         err = tegra_dc_rgb_exit(dc);
2106         if (err) {
2107                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2108                 return err;
2109         }
2110
2111         host1x_client_iommu_detach(client, dc->group);
2112         host1x_syncpt_free(dc->syncpt);
2113
2114         return 0;
2115 }
2116
2117 static const struct host1x_client_ops dc_client_ops = {
2118         .init = tegra_dc_init,
2119         .exit = tegra_dc_exit,
2120 };
2121
2122 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2123         .supports_background_color = false,
2124         .supports_interlacing = false,
2125         .supports_cursor = false,
2126         .supports_block_linear = false,
2127         .has_legacy_blending = true,
2128         .pitch_align = 8,
2129         .has_powergate = false,
2130         .coupled_pm = true,
2131         .has_nvdisplay = false,
2132         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2133         .primary_formats = tegra20_primary_formats,
2134         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2135         .overlay_formats = tegra20_overlay_formats,
2136         .modifiers = tegra20_modifiers,
2137         .has_win_a_without_filters = true,
2138         .has_win_c_without_vert_filter = true,
2139 };
2140
2141 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2142         .supports_background_color = false,
2143         .supports_interlacing = false,
2144         .supports_cursor = false,
2145         .supports_block_linear = false,
2146         .has_legacy_blending = true,
2147         .pitch_align = 8,
2148         .has_powergate = false,
2149         .coupled_pm = false,
2150         .has_nvdisplay = false,
2151         .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2152         .primary_formats = tegra20_primary_formats,
2153         .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2154         .overlay_formats = tegra20_overlay_formats,
2155         .modifiers = tegra20_modifiers,
2156         .has_win_a_without_filters = false,
2157         .has_win_c_without_vert_filter = false,
2158 };
2159
2160 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2161         .supports_background_color = false,
2162         .supports_interlacing = false,
2163         .supports_cursor = false,
2164         .supports_block_linear = false,
2165         .has_legacy_blending = true,
2166         .pitch_align = 64,
2167         .has_powergate = true,
2168         .coupled_pm = false,
2169         .has_nvdisplay = false,
2170         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2171         .primary_formats = tegra114_primary_formats,
2172         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2173         .overlay_formats = tegra114_overlay_formats,
2174         .modifiers = tegra20_modifiers,
2175         .has_win_a_without_filters = false,
2176         .has_win_c_without_vert_filter = false,
2177 };
2178
2179 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2180         .supports_background_color = true,
2181         .supports_interlacing = true,
2182         .supports_cursor = true,
2183         .supports_block_linear = true,
2184         .has_legacy_blending = false,
2185         .pitch_align = 64,
2186         .has_powergate = true,
2187         .coupled_pm = false,
2188         .has_nvdisplay = false,
2189         .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2190         .primary_formats = tegra124_primary_formats,
2191         .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2192         .overlay_formats = tegra124_overlay_formats,
2193         .modifiers = tegra124_modifiers,
2194         .has_win_a_without_filters = false,
2195         .has_win_c_without_vert_filter = false,
2196 };
2197
2198 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2199         .supports_background_color = true,
2200         .supports_interlacing = true,
2201         .supports_cursor = true,
2202         .supports_block_linear = true,
2203         .has_legacy_blending = false,
2204         .pitch_align = 64,
2205         .has_powergate = true,
2206         .coupled_pm = false,
2207         .has_nvdisplay = false,
2208         .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2209         .primary_formats = tegra114_primary_formats,
2210         .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2211         .overlay_formats = tegra114_overlay_formats,
2212         .modifiers = tegra124_modifiers,
2213         .has_win_a_without_filters = false,
2214         .has_win_c_without_vert_filter = false,
2215 };
2216
2217 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2218         {
2219                 .index = 0,
2220                 .dc = 0,
2221                 .windows = (const unsigned int[]) { 0 },
2222                 .num_windows = 1,
2223         }, {
2224                 .index = 1,
2225                 .dc = 1,
2226                 .windows = (const unsigned int[]) { 1 },
2227                 .num_windows = 1,
2228         }, {
2229                 .index = 2,
2230                 .dc = 1,
2231                 .windows = (const unsigned int[]) { 2 },
2232                 .num_windows = 1,
2233         }, {
2234                 .index = 3,
2235                 .dc = 2,
2236                 .windows = (const unsigned int[]) { 3 },
2237                 .num_windows = 1,
2238         }, {
2239                 .index = 4,
2240                 .dc = 2,
2241                 .windows = (const unsigned int[]) { 4 },
2242                 .num_windows = 1,
2243         }, {
2244                 .index = 5,
2245                 .dc = 2,
2246                 .windows = (const unsigned int[]) { 5 },
2247                 .num_windows = 1,
2248         },
2249 };
2250
2251 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2252         .supports_background_color = true,
2253         .supports_interlacing = true,
2254         .supports_cursor = true,
2255         .supports_block_linear = true,
2256         .has_legacy_blending = false,
2257         .pitch_align = 64,
2258         .has_powergate = false,
2259         .coupled_pm = false,
2260         .has_nvdisplay = true,
2261         .wgrps = tegra186_dc_wgrps,
2262         .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2263 };
2264
2265 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2266         {
2267                 .index = 0,
2268                 .dc = 0,
2269                 .windows = (const unsigned int[]) { 0 },
2270                 .num_windows = 1,
2271         }, {
2272                 .index = 1,
2273                 .dc = 1,
2274                 .windows = (const unsigned int[]) { 1 },
2275                 .num_windows = 1,
2276         }, {
2277                 .index = 2,
2278                 .dc = 1,
2279                 .windows = (const unsigned int[]) { 2 },
2280                 .num_windows = 1,
2281         }, {
2282                 .index = 3,
2283                 .dc = 2,
2284                 .windows = (const unsigned int[]) { 3 },
2285                 .num_windows = 1,
2286         }, {
2287                 .index = 4,
2288                 .dc = 2,
2289                 .windows = (const unsigned int[]) { 4 },
2290                 .num_windows = 1,
2291         }, {
2292                 .index = 5,
2293                 .dc = 2,
2294                 .windows = (const unsigned int[]) { 5 },
2295                 .num_windows = 1,
2296         },
2297 };
2298
2299 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2300         .supports_background_color = true,
2301         .supports_interlacing = true,
2302         .supports_cursor = true,
2303         .supports_block_linear = true,
2304         .has_legacy_blending = false,
2305         .pitch_align = 64,
2306         .has_powergate = false,
2307         .coupled_pm = false,
2308         .has_nvdisplay = true,
2309         .wgrps = tegra194_dc_wgrps,
2310         .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2311 };
2312
2313 static const struct of_device_id tegra_dc_of_match[] = {
2314         {
2315                 .compatible = "nvidia,tegra194-dc",
2316                 .data = &tegra194_dc_soc_info,
2317         }, {
2318                 .compatible = "nvidia,tegra186-dc",
2319                 .data = &tegra186_dc_soc_info,
2320         }, {
2321                 .compatible = "nvidia,tegra210-dc",
2322                 .data = &tegra210_dc_soc_info,
2323         }, {
2324                 .compatible = "nvidia,tegra124-dc",
2325                 .data = &tegra124_dc_soc_info,
2326         }, {
2327                 .compatible = "nvidia,tegra114-dc",
2328                 .data = &tegra114_dc_soc_info,
2329         }, {
2330                 .compatible = "nvidia,tegra30-dc",
2331                 .data = &tegra30_dc_soc_info,
2332         }, {
2333                 .compatible = "nvidia,tegra20-dc",
2334                 .data = &tegra20_dc_soc_info,
2335         }, {
2336                 /* sentinel */
2337         }
2338 };
2339 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2340
2341 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2342 {
2343         struct device_node *np;
2344         u32 value = 0;
2345         int err;
2346
2347         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2348         if (err < 0) {
2349                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2350
2351                 /*
2352                  * If the nvidia,head property isn't present, try to find the
2353                  * correct head number by looking up the position of this
2354                  * display controller's node within the device tree. Assuming
2355                  * that the nodes are ordered properly in the DTS file and
2356                  * that the translation into a flattened device tree blob
2357                  * preserves that ordering this will actually yield the right
2358                  * head number.
2359                  *
2360                  * If those assumptions don't hold, this will still work for
2361                  * cases where only a single display controller is used.
2362                  */
2363                 for_each_matching_node(np, tegra_dc_of_match) {
2364                         if (np == dc->dev->of_node) {
2365                                 of_node_put(np);
2366                                 break;
2367                         }
2368
2369                         value++;
2370                 }
2371         }
2372
2373         dc->pipe = value;
2374
2375         return 0;
2376 }
2377
2378 static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2379 {
2380         struct tegra_dc *dc = dev_get_drvdata(dev);
2381         unsigned int pipe = (unsigned long)data;
2382
2383         return dc->pipe == pipe;
2384 }
2385
2386 static int tegra_dc_couple(struct tegra_dc *dc)
2387 {
2388         /*
2389          * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2390          * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2391          * POWER_CONTROL registers during CRTC enabling.
2392          */
2393         if (dc->soc->coupled_pm && dc->pipe == 1) {
2394                 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2395                 struct device_link *link;
2396                 struct device *partner;
2397
2398                 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2399                                              tegra_dc_match_by_pipe);
2400                 if (!partner)
2401                         return -EPROBE_DEFER;
2402
2403                 link = device_link_add(dc->dev, partner, flags);
2404                 if (!link) {
2405                         dev_err(dc->dev, "failed to link controllers\n");
2406                         return -EINVAL;
2407                 }
2408
2409                 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2410         }
2411
2412         return 0;
2413 }
2414
2415 static int tegra_dc_probe(struct platform_device *pdev)
2416 {
2417         struct resource *regs;
2418         struct tegra_dc *dc;
2419         int err;
2420
2421         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2422         if (!dc)
2423                 return -ENOMEM;
2424
2425         dc->soc = of_device_get_match_data(&pdev->dev);
2426
2427         INIT_LIST_HEAD(&dc->list);
2428         dc->dev = &pdev->dev;
2429
2430         err = tegra_dc_parse_dt(dc);
2431         if (err < 0)
2432                 return err;
2433
2434         err = tegra_dc_couple(dc);
2435         if (err < 0)
2436                 return err;
2437
2438         dc->clk = devm_clk_get(&pdev->dev, NULL);
2439         if (IS_ERR(dc->clk)) {
2440                 dev_err(&pdev->dev, "failed to get clock\n");
2441                 return PTR_ERR(dc->clk);
2442         }
2443
2444         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2445         if (IS_ERR(dc->rst)) {
2446                 dev_err(&pdev->dev, "failed to get reset\n");
2447                 return PTR_ERR(dc->rst);
2448         }
2449
2450         /* assert reset and disable clock */
2451         err = clk_prepare_enable(dc->clk);
2452         if (err < 0)
2453                 return err;
2454
2455         usleep_range(2000, 4000);
2456
2457         err = reset_control_assert(dc->rst);
2458         if (err < 0)
2459                 return err;
2460
2461         usleep_range(2000, 4000);
2462
2463         clk_disable_unprepare(dc->clk);
2464
2465         if (dc->soc->has_powergate) {
2466                 if (dc->pipe == 0)
2467                         dc->powergate = TEGRA_POWERGATE_DIS;
2468                 else
2469                         dc->powergate = TEGRA_POWERGATE_DISB;
2470
2471                 tegra_powergate_power_off(dc->powergate);
2472         }
2473
2474         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2475         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2476         if (IS_ERR(dc->regs))
2477                 return PTR_ERR(dc->regs);
2478
2479         dc->irq = platform_get_irq(pdev, 0);
2480         if (dc->irq < 0) {
2481                 dev_err(&pdev->dev, "failed to get IRQ\n");
2482                 return -ENXIO;
2483         }
2484
2485         err = tegra_dc_rgb_probe(dc);
2486         if (err < 0 && err != -ENODEV) {
2487                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2488                 return err;
2489         }
2490
2491         platform_set_drvdata(pdev, dc);
2492         pm_runtime_enable(&pdev->dev);
2493
2494         INIT_LIST_HEAD(&dc->client.list);
2495         dc->client.ops = &dc_client_ops;
2496         dc->client.dev = &pdev->dev;
2497
2498         err = host1x_client_register(&dc->client);
2499         if (err < 0) {
2500                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2501                         err);
2502                 return err;
2503         }
2504
2505         return 0;
2506 }
2507
2508 static int tegra_dc_remove(struct platform_device *pdev)
2509 {
2510         struct tegra_dc *dc = platform_get_drvdata(pdev);
2511         int err;
2512
2513         err = host1x_client_unregister(&dc->client);
2514         if (err < 0) {
2515                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2516                         err);
2517                 return err;
2518         }
2519
2520         err = tegra_dc_rgb_remove(dc);
2521         if (err < 0) {
2522                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2523                 return err;
2524         }
2525
2526         pm_runtime_disable(&pdev->dev);
2527
2528         return 0;
2529 }
2530
2531 #ifdef CONFIG_PM
2532 static int tegra_dc_suspend(struct device *dev)
2533 {
2534         struct tegra_dc *dc = dev_get_drvdata(dev);
2535         int err;
2536
2537         err = reset_control_assert(dc->rst);
2538         if (err < 0) {
2539                 dev_err(dev, "failed to assert reset: %d\n", err);
2540                 return err;
2541         }
2542
2543         if (dc->soc->has_powergate)
2544                 tegra_powergate_power_off(dc->powergate);
2545
2546         clk_disable_unprepare(dc->clk);
2547
2548         return 0;
2549 }
2550
2551 static int tegra_dc_resume(struct device *dev)
2552 {
2553         struct tegra_dc *dc = dev_get_drvdata(dev);
2554         int err;
2555
2556         if (dc->soc->has_powergate) {
2557                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2558                                                         dc->rst);
2559                 if (err < 0) {
2560                         dev_err(dev, "failed to power partition: %d\n", err);
2561                         return err;
2562                 }
2563         } else {
2564                 err = clk_prepare_enable(dc->clk);
2565                 if (err < 0) {
2566                         dev_err(dev, "failed to enable clock: %d\n", err);
2567                         return err;
2568                 }
2569
2570                 err = reset_control_deassert(dc->rst);
2571                 if (err < 0) {
2572                         dev_err(dev, "failed to deassert reset: %d\n", err);
2573                         return err;
2574                 }
2575         }
2576
2577         return 0;
2578 }
2579 #endif
2580
2581 static const struct dev_pm_ops tegra_dc_pm_ops = {
2582         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2583 };
2584
2585 struct platform_driver tegra_dc_driver = {
2586         .driver = {
2587                 .name = "tegra-dc",
2588                 .of_match_table = tegra_dc_of_match,
2589                 .pm = &tegra_dc_pm_ops,
2590         },
2591         .probe = tegra_dc_probe,
2592         .remove = tegra_dc_remove,
2593 };